Luis A. Montalvo

Radix 2 division with over-redundant quotient selection

In this paper we present a new radix 2 division algorithm that uses a recurrence employing simple 3-to-2 digit carry-free adders to perform carry-free addition/subtraction for computing the partial remainders in radix 2 signed-digit form. The quotient digit, during any iteration of the division recursion, is generated from the two most-significant radix 2 digits of the partial remainder and independent of the divisor in over-redundant radix 2 digit form (i.e., with digits which belong to the digit set {-2, -1, 0, +1, +2}). The over-redundant quotient digits are then converted to the conventional radix 2 digits (belonging to the set {-1, 0, +1}) by using a reduction technique. This division algorithm is well suited for IEEE 754 standard operands belonging to the range (1, 2) and is slightly faster than previously proposed radix 2 designs (such as the radix 2 SRT), which do not employ input scaling, since the quotient selection for such algorithms is a function of more than two most-significant radix 2 digits of the partial remainder. In comparison with the designs that employ input scaling, the proposed design although slightly slower saves hardware required for scaling purposes.

Estimation of average energy consumption of ripple-carry adder based on average length carry chains

We show theoretically that the average energy consumption of a ripple-carry adder is O(W), and the upper bound on the average energy consumption is O(Wlog/sub 2/W), where W is the word-length of the operands. Our theoretical analysis is based on a simple state transition diagram (STD) model of a full adder cell and the observations that the average length of a carry propagation chain is v=2, and the average length of the maximum carry chain is v/spl les/log/sub 2/W. To verify our theoretical conclusions, we use the HEAT CAD tool to estimate the average power consumed by the ripple-carry adder for word-lengths 4/spl les/W/spl les/64. The experimental results show that, for W/spl ges/16, the error in our theoretical estimations is around 15%.

Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers

The digit-recurrence division relies on a sequence of addition/subtraction and shift operations in a manner similar to the paper-and-pencil approach, that gives a very regular structure suitable for efficient VLSI implementation. Speed is obtained through the use of redundant number notation allowing carry-propagation-free addition/subtraction with a delay independent of the size of the divisor. Since the quotient digits are obtained sequentially, the delay can theoretically be further reduced by recurring to higher-order radixes to obtain several quotient bits at once. This paper compares the synthesis of radix-2 and radix-4 dividers.

Svoboda-Tung division with no compensation

The development of a new general radix-b division algorithm, based on the Svoboda-Tung division, suitable for VLSI implementation is presented. The new algorithm overcomes the drawbacks of the Svoboda-Tung techniques that have prevented the VLSI implementation. First of all, the proposed algorithm is valid for any radix b/spl ges/2; and next, it avoids the possible compensation due to overflow on the iteration by re-writing the two most significant digits of the remainder. An analysis of the algorithm shows that a known radix-2 and two recently published radix-4 division algorithms are particular cases of this general radix-b algorithm. Finally, since the new algorithm is valid only for a reduced range of the IEEE normalised divisor, a pre-scaling technique, based on the multiplication of both the operands by a stepwise approximation to the reciprocal of the divisor is also presented,.

Application of fast layout synthesis environment to dividers evaluation

Experience has shown that generator programs are quite often written by VLSI designers, as they hold the empirical knowledge better than anyone. However, their ability does not necessarily include programming and debugging skills: these designers have to focus on the problem at hand not on the tools or the language they use to solve it. GenOptim has been created to quickly design efficient IEEE 754 floating-point macro-cell generators that do not rely on particular target technologies. Whereas the design of fast and efficient adders, multipliers and shifters is well understood division and square root remain a serious design challenge. GenOptim was used to quickly evaluate new divider architectures.<<ETX>>

Radix-2 over-redundant digit set converters

Often radix-2 division algorithms make use of over redundant digit-set in the selection of the quotient digits. The final step in such a division algorithm is the conversion of the quotient to the conventional twos complement notation. The best approach for this conversion, in the case of non-over-redundant digit sets, is the on-the-fly technique. In this paper, we explore two different alternatives to the on-the-fly conversion algorithm, for the conversion of an integer number from the radix-2 over-redundant representation into the twos complement notation. In the direct conversion approach, the conversion is realized in one step. In the redundancy reduction approach, the conversion is achieved in two steps: a redundancy reduction step and a binary conversion step. The discussion is carried out assuming no restrictions on the sequence of radix-2 over-redundant digits. Our main conclusion is that the redundancy reduction approach is the most efficient.