Jang-hi Im

Significance of coating stress on substrate bow in large area processing of MCM

The substrate bow in a large area processing (LAP) was simulated using a finite element analysis (FEA). The structures considered were aluminum (Al) and glass substrates of various thicknesses, and a coating from photosensitive film thickness. It was found that the deflection of a large area substrate, e.g. 400 mm square, could not always be obtained from the linear, small deflection theory even if the curvature might be small and the stress-strain behavior in the linear elastic regime. In this case, the nonlinear, large deflection theory had to be adopted. Also, the gravity effect on the weight of substrate turned out to be very significant and had to be incorporated as well. The simulation incorporating these two factors agreed well with the experimental data, which was generated by spin coating and curing the BCB formulation on Al substrates, 400/spl times/400/spl times/1.27 mm. As a means of flattening out the curvature, subjecting a vacuum underneath the substrate was simulated. Significant reduction of the substrate deflection was observed by applying only a very small vacuum. This result suggested that the use of double-stick tape on the bottom of the substrate, for example, might also be feasible to completely eliminate the bow.

A novel positive-tone and aqueous-base-developable photosensitive benzocyclobutene-based material for microelectronics

This work describes a positive-tone and aqueous-base-developable benzocyclobutene (BCB)-based dielectric material. The polymer is made from divinylsiloxane bis(benzocyclobutene) and BCB-acrylic acid. A diazonap-thoquinone in the formulation makes it photosensitive. Patterned films have high resolution, and via openings are scum-free without a de-scum operation. The material possesses optical, electrical, thermal, and mechanical properties desirable for many microelectronic applications, including as a planarization layer or an insulation layer in display, and in packaging.

Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects

The thermomechanical reliability of Cu/low-k interconnects, which is directly related to yield problems and premature device failures, has been a major issue. The development of a manufacturing process, which can satisfy the most stringent reliability standards, requires detailed information on the thermomechanical behavior of Cu/low-k interconnects. The thermomechanical behavior of Cu/low-k interconnects is complicated by the fact that processinduced thermal stresses are developed during the manufacturing process. A conventional finite element analysis (FEA) approach has some difficulties to model Cu/low-k interconnects that keep changing during process steps. Therefore, a sequential process modeling technique has been developed to simulate the interconnect behavior to substantially any level of detail and understand the complex thermomechanical behavior of Cu/low-k interconnects while being manufactured. In this paper, we briefly describe a sequential process modeling technique and demonstrate how we use the modeling technique to solve a Cu/SiC delamination problem in a Cu/SiLK* semiconductor dielectric dual damascene test structure.

Mechanical Properties of Cured SiLK Low-K Dielectric Films

SiLK (trademark of The Dow Chemical Company) semiconductor dielectric is a low-k organic polymer, based on the synthesis of crosslinked polyphenylenes by the reaction of poly functional cyclopentadienone- and acetylene-containing materials1. SiLK dielectric is used for high performance integrated circuits with subtractive Al/W 2–4 or Cu damascene 5–7 wiring technology. The properties of cured SiLK enable integration with current interlayer dielectric (ILD) processes: for example, high thermal stability, high Tg, low dielectric constant, no fluorine, spin-on application, good adhesion and mechanical durability, low moisture absorption, and solvent resistance. Some of these properties are listed in Table 1.