Jang-Won Park

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. When the proposed VL-ECC is applied to the embedded memory devices of an H.264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB.

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.

Reconfigurable ECC for adaptive protection of memory

Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundancy) remain effective in healing manufacturing defects and process variation induced failures in nanoscale memory. They are, however, not effective in improving robustness under various run-time failures. Increasing run-time failures in memory, specifically in case of low-voltage low-power memory, has emerged as a major design challenge. Traditionally, a uniform worst-case protection using Error Correction Code (ECC) is used for all blocks in a large memory array for runt-time error resiliency. However, with both spatial and temporal shift in intrinsic reliability of a memory block, such uniform protection can be unattractive in terms of either ECC overhead or protection level. We propose a novel Reconfigurable ECC approach, which can adapt, in space and time, to varying reliability of memory blocks by using an ECC that can provide the right amount of protection for a memory block at a given time. We show that such an approach is extremely effective in diverse applications.

Adaptive ECC for Tailored Protection of Nanoscale Memory

Editor’s note: Following technology scaling, runtime failure has emerged as one of the major challenges in modern VLSI designs under the increased parametric variability and low supply voltage. This issue is especially severe in nanoscale memory due to its high density and large capacity. In this work the authors present a novel reconfigurable Error Correction Code (ECC) to improve the reliability of nanoscale memory. —Yiran Chen, University of Pittsburgh