Jongsun Park

An Adaptive Impedance-Matching Network Based on a Novel Capacitor Matrix for Wireless Power Transfer

In a wireless power transfer (WPT) system via the magnetic resonant coupling, one of the most challenging design issues is to maintain a reasonable level of power transfer efficiency (PTE), even when the distance between the transmitter and the receiver changes. When the distance varies, the PTE drastically decreases due to the impedance mismatch between the resonator of the transmitter and that of the receiver. This paper presents a novel serial/parallel capacitor matrix in the transmitter, where the impedance can be automatically reconfigured to track the optimum impedance-matching point in the case of varying distances. The dynamic WPT matching system is enabled by changing the combination of serial and parallel capacitors in the capacitor matrix. An interesting observation in the proposed capacitor matrix is that the resonant frequency is not shifted, even with capacitor-matrix tuning. In order to quickly find the best capacitor combination that achieves maximum power transfer, a window-prediction-based search algorithm is also presented in this paper. The proposed resonance WPT system is implemented using a resonant frequency of 13.56 MHz, and the experimental results with 1W power transfer show that the transfer efficiency increases up to 88 % when the distance changes from 0 to 1.2 m.

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chips core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.

A Highly Sensitive Capacitive Touch Sensor Integrated on a Thin-Film-Encapsulated Active-Matrix OLED for Ultrathin Displays

This paper presents ultrathin and highly sensitive input/output devices consisting of a capacitive touch sensor (Cap-TSP) integrated on thin-film-encapsulated active-matrix organic light-emitting diodes (OLEDs). The optimal structure of the electrically noise-free capacitive touch sensor, which is assembled on a thin-film-encapsulated active-matrix OLED (AMOLED) display, is obtained by investigating the internal electrical field distribution and capacitance change based on the Q3D Extractor model. Electrostatic simulations have verified malfunction-free electrical signals for 4-in diagonal-sized capacitive touch sensors on AMOLEDs possessing a 100-μm-thick optically clear adhesive (OCA, εr = 1.4) layer. The prototype OLED platform using the capacitive touch sensors exhibits an overall thickness of 1.2 mm, which is the lowest thickness for commercially available OLED platforms.

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

This paper presents a dynamic bit-width adaptation scheme for applications using discrete cosine transform (DCT). The technique can efficiently trade off image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, separate operand bit-widths are used for different frequency components to reduce computation energy. To select the appropriate operand bit-widths that achieve significant reduction of power consumption with minimum image quality degradation, we also propose a bit-width selection algorithm. The proposed variable bit precision DCT algorithm can be efficiently implemented using carry save adder trees. The reconfigurable DCT architecture can achieve power savings ranging from 36% to 75% compared to normal operation at the expense of minor image quality degradation.

Fully transparent pixel circuits driven by random network carbon nanotube transistor circuitry

Optically transparent and mechanically flexible thin-film transistors have recently attracted attention for next generation transparent display technologies. Driving and switching transistors for transparent displays have challenging requirements such as high optical transparency, large-scale integration, suitable drive current (I(on)) in the microampere range, high on/off current ratio (I(on)/I(off)), high field-effect mobility, and uniform threshold voltage (V(th)). In this study, we demonstrate fully transparent high-performance and high-yield thin-film transistors based on random growth of a single-walled carbon nanotube (SWNT) network that are easy to fabricate. High-performance SWNT-TFTs exhibit optical transmission of 80% in visible wavelength, I(on)/I(off) higher than 10(3), and a high yield with reproducible electrical characteristics.

Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers

A wavelet Electrocardiogram (ECG) detector for low-power implantable cardiac pacemakers is presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. In order to achieve high detection accuracy with low power consumption, a multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited in our ECG detector implementation. Our algorithmic and architectural level approaches have been implemented and fabricated in a standard 0.35 μm CMOS technology. The testchip including a low-power analog-to-digital converter (ADC) shows a low detection error-rate of 0.196% and low power consumption of 19.02 μW with a 3 V supply voltage.

A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption

This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.

High-performance FIR filter design based on sharing multiplication

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.

A distributed MAC design for data collision-free wireless USB home networks

USB has been used at an enormous number of USB devices as a universal interface. Advances in USB and wireless communication technologies have led USB-IF (USB Implementers Forum) to establishment of WUSB(Wireless USB) standard 1.0 that has wired USBs speed and compatibility in addition to wireless technologys convenience. The wireless USB provides convenience. However, due to mobility of WUSB devices in multi-hop environment, DRP (Distributed Reservation Protocol) reservation conflicts happen frequently among devices with three-hop distance. To solve this problem, we propose a new DRP reservation scheme using a new 2-hop range DRP Availability IE for three-hop mobility support in WUSB networks with ultrawideband (UWB) technology. It is shown by simulation results that throughputs of devices at frequent three-hop range DRP reservation conflicts are largely increased.

Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM memory is still designed without considering the importance differences found among the data stored in the SRAM bit-cells. This paper presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allows us to obtain the better video quality even in lower voltage operation. In order to find the SRAM bit-cell sizes that achieve the best video quality under SRAM area constraint, we propose a heterogeneous SRAM sizing algorithm based on a dynamic programming. Compared to the brute-force search, the proposed algorithm greatly reduces the computation time needed to select the SRAM bit-cell sizes of 8 bit pixel. Experimental results show that under iso-area condition, the heterogeneous SRAM array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared to the conventional one with identical cell sizing.