Jang Woong Park

Simplified soft-decision demapping algorithm for DVB-S2

This paper presents a simplified soft-decision demapping algorithm for Digital Video Broadcasting via satellite, Second Generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) code decoder, the received signal should be soft-decided rather than hard-decided. However, the soft-decision demapper requires high hardware complexity to support higher-order modulation modes. The proposed soft-decision demapping algorithm can reduce computation complexity by eliminating a square operation. In addition, simulation results show that the proposed algorithm has negligible performance degradation compared with the conventional algorithms.

Low complexity soft-decision demapper for high order modulation of DVB-S2 system

This paper presents an efficient soft-decision demapper interface and a low complexity demapper for high-order modulation scheme. The proposed soft-decision demapper interface can operate at a symbol rate and replace the parallel to serial converter by locating between the M-PSK demodulator and the soft-decision demapper. In addition, the proposed soft-decision demapper can reduce the hardware complexity by reusing the multipliers. Moreover, the proposed demapper can support high-order modulation modes. The proposed architectures have been thoroughly verified using a FPGA board having the the Xilinxtrade Virtex II.

An Efficient Data-Aided Initial Frequency Synchronizer for DVB-S2

This paper presents an efficient initial frequency synchronizer for DVB-S2. An initial frequency offset of the DVB-S2 is around ±5 MHz, which represents 20% of the symbol rate at 25 Mbaud. To estimate a large initial frequency offset, the algorithm which can provide a large estimation range is required. Through the analysis of the Data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Based on the algorithm, we propose an efficient initial frequency synchronizer to reduce hardware complexity. The proposed architecture can reduce about 68% multipliers, 55% arctan units and 54% adder/subtractors compared with the direct implementation. The proposed architecture has been thoroughly verified using a FPGA board having the the XilinxTM Virtex II.

Efficient coarse frequency synchronizer using serial correlator for DVB-S2

This paper proposes an efficient coarse frequency synchronizer for digital video broadcasting - second generation (DVB-S2). The input signal requirement of acquisition range for coarse frequency estimator in the DVB-S2 is around plusmn1.5625 Mhz, which corresponds to 6.25% of the symbol rate at 25 M baud. At the process of analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most promising one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.

Data-aided algorithm based frequency synchronizer for DVB-S2

This paper presents an efficient frequency synchronizer for digital video broadcasting --- second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute ouput values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.

Enhanced Degree Computationless Modified Euclid's Algorithm

This paper proposes an enhanced degree computationless modified Euclids (E-DCME) algorithm for Reed-Solomon decoder. The proposed E-DCME algorithm can reduce the number of multiplexers compared with the existing DCME algorithm. The critical path delay of the proposed E-DCME algorithm requires only TMul + TADD + TMUX while that of the existing DCME algorithm requires TMul + TADD + 2TMUX. In addition the proposed E-DCME algorithm uses 3t basic cells and has the latency of 2t -1 clock cycles for solving the key equation. However, the existing DCME algorithm requires 3t + 2 basic cells and 2t clock cycles for solving the key equation. The gate count of the proposed E-DCME architecture is 17,840. Therefore, the E-DCME architecture can reduce the gate count about 18% compared with the existing DCME architecture

Multi-level modulation soft-decision demapper for DVB-S2

This paper presents a low complexity soft-decision demapper for the Digital Video Broadcasting - Satellite second generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) code decoder, the received signal should be soft-decided rather than hard-decided. However, the softdecision demapper requires high hardware complexity to support higher-order modulation modes. The proposed soft-decision demapper can reduce the hardware complexity by reusing multipliers. In addition, we propose an efficient soft-decision demapper interface that can operate at a symbol rate and we can replace a Parallel to Serial (P/S) converter with the proposed interface by locating between an M-Phase Shift Keying (PSK) demodulator and the proposed demapper. The proposed soft-decision demapper and and its interface have been verified in XilinxTM Virtex II.

Low complexity synchronizer architecture based on common autocorrelator for Digital Video Broadcasting system

This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in Xilinx™ Virtex IV and R&S™ SFU (Signaling and Formatting Unit) broadcast test equipment.

Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system

This paper presents an efficient frequency estimator for digital video broadcasting - second generation (DVB-S2). Analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most suitable one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency estimator can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.