Pan Soo Kim

Simplified soft-decision demapping algorithm for DVB-S2

This paper presents a simplified soft-decision demapping algorithm for Digital Video Broadcasting via satellite, Second Generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) code decoder, the received signal should be soft-decided rather than hard-decided. However, the soft-decision demapper requires high hardware complexity to support higher-order modulation modes. The proposed soft-decision demapping algorithm can reduce computation complexity by eliminating a square operation. In addition, simulation results show that the proposed algorithm has negligible performance degradation compared with the conventional algorithms.

Low complexity soft-decision demapper for high order modulation of DVB-S2 system

This paper presents an efficient soft-decision demapper interface and a low complexity demapper for high-order modulation scheme. The proposed soft-decision demapper interface can operate at a symbol rate and replace the parallel to serial converter by locating between the M-PSK demodulator and the soft-decision demapper. In addition, the proposed soft-decision demapper can reduce the hardware complexity by reusing the multipliers. Moreover, the proposed demapper can support high-order modulation modes. The proposed architectures have been thoroughly verified using a FPGA board having the the Xilinxtrade Virtex II.

An Efficient Data-Aided Initial Frequency Synchronizer for DVB-S2

This paper presents an efficient initial frequency synchronizer for DVB-S2. An initial frequency offset of the DVB-S2 is around ±5 MHz, which represents 20% of the symbol rate at 25 Mbaud. To estimate a large initial frequency offset, the algorithm which can provide a large estimation range is required. Through the analysis of the Data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Based on the algorithm, we propose an efficient initial frequency synchronizer to reduce hardware complexity. The proposed architecture can reduce about 68% multipliers, 55% arctan units and 54% adder/subtractors compared with the direct implementation. The proposed architecture has been thoroughly verified using a FPGA board having the the XilinxTM Virtex II.

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.

Low complexity soft-decision demapper for DVB-S2 using phase selection method

This paper presents a simplified soft-decision demapping algorithm using the phase selection method for Digital Video Broadcasting via satellite Second Generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) decoder and support higher-order modulation modes, the soft-decision demapper should require high hardware complexity. The proposed soft-decision demapping algorithm can reduce computation complexity by eliminating square operations. In addition, simulation results show that the proposed algorithm has negligible performance degradation compared with the conventional algorithms. Moreover, the proposed soft-decision demapper has been verified using the Virtex IV-LX 200 FPGA board. Comparing with the direct implementation, the proposed demapper can reduce about 81% hardware resources.

Multi-level modulation soft-decision demapper for DVB-S2

This paper presents a low complexity soft-decision demapper for the Digital Video Broadcasting - Satellite second generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) code decoder, the received signal should be soft-decided rather than hard-decided. However, the softdecision demapper requires high hardware complexity to support higher-order modulation modes. The proposed soft-decision demapper can reduce the hardware complexity by reusing multipliers. In addition, we propose an efficient soft-decision demapper interface that can operate at a symbol rate and we can replace a Parallel to Serial (P/S) converter with the proposed interface by locating between an M-Phase Shift Keying (PSK) demodulator and the proposed demapper. The proposed soft-decision demapper and and its interface have been verified in XilinxTM Virtex II.

Low complexity synchronizer architecture based on common autocorrelator for Digital Video Broadcasting system

This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in Xilinx™ Virtex IV and R&S™ SFU (Signaling and Formatting Unit) broadcast test equipment.