Jani Boutellier

Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding

The upcoming Reconfigurable Video Coding (RVC) standard from MPEG (ISO / IEC SC29WG11) defines a library of coding tools to specify existing or new compressed video formats and decoders. The coding tool library has been written in a dataflow/actor-oriented language named CAL. Each coding tool (actor) can be represented with an extended finite state machine and the data communication between the tools are described as dataflow graphs. This paper proposes an approach to model the CAL actor network with Parameterized Synchronous Data Flow and to derive a quasi-static multiprocessor execution schedule for the system. In addition to proposing a scheduling approach for RVC, an extension to the well-known permutation flow shop scheduling problem that enables rapid run-time scheduling of RVC tasks, is introduced.

Mobile transmitter digital predistortion: Feasibility analysis, algorithms and design exploration

This article addresses intermodulation challenges in carrier aggregation (CA) and multicluster type transmission scenarios in mobile transmitters. In such transmission schemes, emerging in 3GPP LTE-Advanced mobile cellular radio evolution, the spectrum of the signal entering the transmit power amplifier (PA) is of non-contiguous nature and thus severe intermodulation is created which may violate the spurious emission mask. To satisfy the stringent emission requirements and limits, devices may need to considerably back off their transmit power, compared to nominal value of ;23dBm, but this will reduce the uplink coverage. As an alternative, feasibility of digital predistortion (DPD) is explored in this article. A DPD solution is developed to control the most critical intermodulation components from terminal emission mask perspective with reduced complexity compared to conventional DPD solutions. The DPD is based on the Augmented Parallel Hammerstein (APH) architecture which can handle IQ imbalance and local oscillator leakage in addition to the PA nonlinearity while using simple digital linear estimation techniques. Furthermore, digital design exploration is carried out for the predistortion algorithm, implying that the needed computational resources are close to what is already available in most advanced mobile platforms and chipsets in the market.

Parameterized Sets of Dataflow Modes And Their Application to Implementation of Cognitive Radio Systems

Cognitive radio networks present challenges at many levels of design, including configuration, control, and cross-layer optimization. To meet requirements of bandwidth, flexibility and reconfigurability, systematic methods to model and analyze cognitive radio designs on signal processing platforms are desired. To help address these challenges, we present in this paper a novel dataflow modeling technique, called parameterized set of modes (PSM). PSMs allow efficient representation, manipulation and application of related groups of processing configurations for functional design components in signal processing systems. PSMs lead to more concise formulations of actor behavior, and a unified modeling methodology for applying a variety of techniques for efficient implementation. We develop the formal foundations of PSM-based modeling, and demonstrate its utility through two case studies involving the mapping of reconfigurable wireless communication functionality into efficient implementations.

Scheduling of dataflow models within the Reconfigurable Video Coding framework

The upcoming reconfigurable video coding (RVC) standard from MPEG (ISO/IEC SC29WG11) defines a library of coding tools to specify existing or new compressed video formats and decoders. The coding tool library has been written in a dataflow/actor-oriented language named CAL. Each coding tool can be represented with an extended finite state machine and the dependencies between the tools are described as dataflow graphs. This paper proposes an approach to derive a multiprocessor execution schedule for RVC systems that are comprised of CAL actors. In addition to proposing a scheduling approach for RVC, an extension to the well-known permutation flow shop scheduling problem that enables rapid run-time scheduling of RVC tasks is introduced.

Evaluation of real-time LBP computing in multiple architectures

Local binary pattern (LBP) is a texture operator that is used in several different computer vision applications requiring, in many cases, real-time operation in multiple computing platforms. The irruption of new video standards has increased the typical resolutions and frame rates, which need considerable computational performance. Since LBP is essentially a pixel operator that scales with image size, typical straightforward implementations are usually insufficient to meet these requirements. To identify the solutions that maximize the performance of the real-time LBP extraction, we compare a series of different implementations in terms of computational performance and energy efficiency, while analyzing the different optimizations that can be made to reach real-time performance on multiple platforms and their different available computing resources. Our contribution addresses the extensive survey of LBP implementations in different platforms that can be found in the literature. To provide for a more complete evaluation, we have implemented the LBP algorithms in several platforms, such as graphics processing units, mobile processors and a hybrid programming model image coprocessor. We have extended the evaluation of some of the solutions that can be found in previous work. In addition, we publish the source code of our implementations.

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.

Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems

In this paper, we present four scheduling algorithms that provide flexible utilization of fine-grain DSP accelerators with low run-time overhead. Methods that have originally been used in operations research are implemented in a way that minimizes the amount of run-time computations. These low overhead scheduling methods can be used for synchronization in multi-processor systems, especially when dedicated co-processors implement tasks with low turnaround times. We demonstrate our methods by an application to MPEG-4 video decoding. In this demonstration, MPEG-4 macroblock decoding is modeled as a permutation flowshop problem and our proposed algorithms are applied to schedule co-processors that implement MPEG-4 block decoding operations. Experimental results demonstrate the effectiveness of our scheduling approach.

Actor Merging for Dataflow Process Networks

Dataflow process networks provide a versatile model of computation for specifying signal processing applications in a platform independent fashion. This attractive feature of dataflow has lately been realized in dataflow programming tools that allow synthesizing the same application specification as both fixed hardware circuits and as software for programmable processors. However, in practice, the specification granularity of the dataflow program remains an arbitrary choice of the designer. Dataflow specifications of the same application with equivalent I/O behaviour can range from a single dataflow actor to a very fine grained network composed of elementary processing operations. A very fine grained dataflow specification might result into a high performance implementation when synthesized as hardware, but might perform poorly when executed on a programmable processor. This article presents actor merging as one solution for this performance portability problem of dataflow programs. In contrast to previous work around actor merging, this article presents a methodology that can merge also dynamic dataflow actors. To support these claims, results of experiments on several processing platforms and application examples ranging from telecommunications to video compression are reported.

Scheduling of CAL actor networks based on dynamic code analysis

CAL is a dataflow oriented language for writing high-level specifications of signal processing applications. The language has recently been standardized and selected for the new MPEG Reconfigurable Video Coding standard.

Objective Evaluation of Image Mosaics

Image stitching is an image processing method, where multiple photographs covering different parts of the same scene, are combined to form a single wide-angle image. Stitching is a very challenging task, and during the past decades many algorithms have been developed for it. Unfortunately, there has been no objective way to measure the quality of stitching results. To mend this shortcoming, we propose a novel method for testing stitching algorithms. The testing process starts from an arbitrary reference image that is used to create synthetic input data for the stitching algorithm that is to be tested. To make the testing realistic, various camera-related distortions along with perspective warps are applied to the input images. From this input data, the stitching algorithm creates a wide-angle image that is then compared to the reference image, from which the process started.