Jar-Shone Ker

Hardware implementation of CMAC neural network with reduced storage requirement

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.

A fuzzy CMAC model for color reproduction

Abstract Color reproduction is a complex nonlinear mapping problem due to gamut mismatch, resolution conversion, quantization, nonlinear color relationship between scanner and printer. To solve such a complex problem in color reproduction, this paper proposes a fuzzy CMAC model, which adopts a special parallel fuzzy inference-like process to realize the function similar to higher-order CMAC. In this model, recursive B-spline receptive field functions are replaced by fuzzy sets with bell-shaped membership function, and the weights to evaluate output values are also not crisp values but fuzzy sets. The learning algorithm is based on the maximum gradient method. For the situations of insufficiently or irregularly distributed training patterns, this paper develops a sampling method to generate uniformly distributed training patterns. According to experimental results, the proposed fuzzy CMAC model has shown its effectiveness on color reproduction and general function approximations. Besides, it has advantages of fast learning speed, simple computation, and high stability on model parameters.

Hardware realization of higher-order CMAC model for color calibration

The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and nonlinearity between scanner and printer is usually recognized as an essential issue of color reproduction. To efficiently calibrate the nonlinearity between scanning/printing devices, we present a linear systolic array architecture to realize the higher-order CMAC neural network model and propose an extended direct weight cell address mapping scheme for weight retrieving. This mapping scheme exhibits fast computation speed in generating weight cell addresses. Some experiments are performed to evaluate the approximation capability of the higher-order CMAC neural network models. It is shown that the CMAC model behaves well for those trained regions over the input space and exhibits smooth approximation for those untrained regions over the input space.

A CMAC neural network chip for color correction

This paper presents the design and implementation of a CMAC neural network chip used in color image reproduction systems for color correction. An effective address mapping procedure is proposed to implement the hardware architecture of CMAC model, which has the advantages of high processing speed and low chip area overhead. VHDL-based high-level synthesis approach is employed for the synthesis of logic circuit of CMAC chip.<<ETX>>

Enhancement of the weight cell utilization for CMAC neural networks: architecture design and hardware implementation

CMAC neural network model has the advantages of fast learning and insensitivity to the order of presentation of training data. However, it may suffer from a huge storage requirement for realizing the weight cell memory. In this paper, we propose a memory banking structure and a direct weight cell address mapping scheme, which can sharply reduce the required address space of weight cell memory. This mapping scheme also exhibits a fast computation speed in generating weight cell addresses. Besides, a pipelined architecture is developed to realize the CMAC chip. To efficiently manage design complexity and increase design productivity and maintainability, a high-level synthesis technique is adopted to perform the task of logic design of the CMAC chip.

FPGA implementation of fuzzy color correction system

In this paper, a color correction system designed by adaptive fuzzy tree inference scheme is proposed to convert the scanner RGB colors into printer CMY colors. For real-time processing, a modular design approach is used to design this correction system, and the prototype of this system has been implemented by employing the methodology of FPGA. Experimental results show that the proposed system exhibits well inference performance with low computation complexity.

Design of a color reproduction neural network chip with on-chip learning capability

The process of eliminating color errors from the gamut mismatch, resolution conversion, quantization and non-linearity between scanner and printer is an essential issue of color reproduction. To efficiently calibrate the non-linear color distortion characteristic between color scanner and printer and to enhance the reproduction quality of color documents, we develop a hardware processing module, which realizes the operation of a higher order CMAC neural network model with linear systolic array architecture, to on-line calibrate the color during the reproducing session. This mapping scheme exhibits fast computation speed in evaluating the output responses of higher-order CMAC model.

A test program generator for memory systems

Abstract A set of algorithms which can be used to detect and locate the faults in a given memory system, and a test program generator which automatically produces test programs according to the algorithms which are used by the memory system to be tested are developed. Furthermore, a fault simulator designed to simulate the faulty behavior of a memory system has been developed to evaluate the effectiveness of the test program in covering faults. Results showed that a fault coverage near 100% could be achieved.

Functional test pattern generation for asynchronous circuits

A functional test generation algorithm is developed. It generates test patterns directly from a graphical model, called the signal transition graph (STG). STG is used for the design and modeling of asynchronous circuits. Emphasis is placed on test generation for asynchronous circuits. A token propagation fault model is proposed to model the fault effects exhibiting on STG. The equivalence/dominance fault collapsing analysis is applied to reduce the number of faults to be considered.<<ETX>>