Bin-Da Liu

Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms

In this paper, we propose a novel fuzzy logic controller, called linguistic hedge fuzzy logic controller, to simplify the membership function constructions and the rule developments. The design methodology of linguistic hedge fuzzy logic controller is a hybrid model based on the concepts of the linguistic hedges and the genetic algorithms. The linguistic hedge operators are used to adjust the shape of the system membership functions dynamically, and ran speed up the control result to fit the system demand. The genetic algorithms are adopted to search the optimal linguistic hedge combination in the linguistic hedge module, According to the proposed methodology, the linguistic hedge fuzzy logic controller has the following advantages: 1) it needs only the simple-shape membership functions rather than the carefully designed ones for characterizing the related variables; 2) it is sufficient to adopt a fewer number of rules for inference; 3) the rules are developed intuitionally without heavily depending on the endeavor of experts; 4) the linguistic hedge module associated with the genetic algorithm enables it to be adaptive; 5) it performs better than the conventional fuzzy logic controllers do; and 6) it can be realized with low design complexity and small hardware overhead. Furthermore, the proposed approach has been applied to design three well-known nonlinear systems. The simulation and experimental results demonstrate the effectiveness of this design.

Urinalysis with molecularly imprinted poly(ethylene-co-vinyl alcohol) potentiostat sensors

Among many important biomarkers excreted in urine are albumin, uric acid, glucose, urea, creatine and creatinine. In the growing elderly population, these biomarkers may be useful correlates with kidney dysfunction, infection and related problems such as glomerular, proximal, and distal convoluted tubule functions, diabetes, hypertension and proteinuria. This study employed solvent evaporation processing of poly(ethylene-co-vinyl alcohol), (EVAL) to form molecularly imprinted polymers (MIPs) that recognize creatinine, urea, and lysozyme. The mole ratio of ethylene to vinyl alcohol affected the performance: 27 mol% ethylene gave the highest imprinting effectiveness for creatinine and urea, while 44 mol% gave the highest effectiveness for lysozyme. Electrochemical examination using a home made potentiostat and imprinted polymer electrode showed electrical signals responsive to the target molecules. Finally, an actual urine sample was tested using the electrode. The test results were compared with those of the commercial instrument ARCHITECT ci 8200 system to precisely determine the accuracy of the molecularly imprinted polymer electrode for urinalysis.

A practical current sensing technique for I/sub DDQ/ testing

In this paper, a practical design for built-in current sensors (BICSs) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard. >

High throughput 2-D transform architectures for H.264 advanced video coders

In this work, high throughput hardware architectures for fast computation of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC) are presented. After complexity and efficiency analyses, we find that the proposed architectures could provide higher throughput rate and realize in a smaller chip area than the conventional row-column approaches. The proposed architectures are synthesized with TSMC 0.35 /spl mu/m technology. The synthesized multiple transform architecture could process 800 M samples/sec at 100 MHz for all the three transforms.

Combined 2-D transform and quantization architectures for H.264 video coders

In this paper, the low-complexity hardware architectures of 4/spl times/4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into the transform step, which results in a reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 /spl mu/m technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in the encoder part and 448 M samples/sec at 56 MHz in the decoder part.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder

In this paper, an efficient algorithm is proposed to improve the decoding efficiency of the context-based adaptive variable length coding (CAVLC) procedure. Due to the data dependency among symbols in the decoding flow, the CAVLC decoder requires large computation time, which dominates the overall decoder system performance. To expedite its decoding speed, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, a low power combined LUT and single output buffer have been adopted to reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard. The maximum frequency can be larger than 210 MHz, which can easily support the real-time requirement for resolutions higher than the HD1080 format.

Recursive architectures for realizing modified discrete cosine transform and its inverse

In this paper, we present efficient recursive architectures for realizing the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) acquired in many audio coding systems. After data rearrangement, the MDCT and IMDCT can be represented as the Chebyshev polynomials such that we can efficiently implement them in the recursive structures. For verification, we design an ASIC to realize the recursive IMDCT. The analyzed results show that the proposed recursive infinite-impulse response (IIR) structures possess advantages of high efficiency and high throughput rate. The high regularity and modularity of the proposed recursive IMDCT and MDCT algorithms are other merits for very large scale integration implementation.

A modular current-mode classifier circuit for template matching application

In this work, a current-mode Euclidean distance calculator circuit is proposed to play the role of a classifier. This classifier circuit is designed based on a subtracter circuit, an absoluter circuit, a squarer/divider circuit, and a square-rooter/multiplier circuit. The modular design of this classifier allows it to be easily extended for classification application with more input dimensions by doing some proper signal-scaling work due to the dynamic range limited by the square-rooter/multiplier circuit. This classifier circuit has been fabricated with a 0.6 /spl mu/m single-polysilicon double-metal CMOS process. Both simulation results and measurements of the implemented chip are presented to confirm the function of this classifier.

Circuit implementation of linguistic-hedge fuzzy logic controller in current-mode approach

In this paper, a novel fuzzy logic controller called linguistic-hedge fuzzy logic controller in a mixed-signal circuit design is discussed. The linguistic-hedge fuzzy logic controller has the following advantages: 1) it needs only three simple-shape membership functions for characterizing each variable prior to the linguistic-hedge modifications; 2) it is sufficient to adopt nine rules for inference; 3) the rules are developed intuitively without heavy dependence on the endeavors of experts; 4) it performs better than conventional fuzzy logic controllers; and 5) it can be realized with a lower design complexity and a smaller hardware overhead as compared with the controllers that required more than nine rules. In this implementation, a current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. This design was fabricated with a TSMC 0.35 /spl mu/m single-polysilicon-quadruple-metal CMOS process. In this chip, the LHFLC processes two input variables and one output variable. Each variable is specified using three membership functions. Nine inference rules, scheduled in a rule table with a dimension of 3 /spl times/ 3, define the relationship implications between these three variables. Under a supply voltage of 3.3 V, the measurement results show that the measured control surface and the control goal are consistent. The speed of inference operation goes up to 0.5M FLIPS that is fast enough for the control application of the cart-pole balance system. The cart-pole balance system experimental results show that this chip works with nine inference rules. Furthermore, by performing some off-chip modifications, such as shifting and scaling on the input signals and output signal of this design, according to the specifications defined by the controlled plants, this design is suitable for many control applications.