Jarbas Silveira

A security aware routing approach for NoC-based MPSoCs

Malicious applications target Multi-Processors System-on-Chip (MPSoCs) to capture sensitive information or disrupt normal operation; therefore, security is now a design requirement for MPSoC design. Network-on-Chip (NoC) is a key communication structure to aid in the overall MPSoC protection. Firewall-based NoC protection allows data exchange monitoring and controlling according to the MPSoC security policy. Secure NoCs enable to detect and prevent a broad range of software-based attacks. However, complex security policies may turn firewalls costly. This paper proposes a protection technique based on the NoC routing algorithm. By manipulating the routing of packets, security zones can be built. Our routing algorithm prioritizes communication among paths deemed secure while guaranteeing deadlock freedom. We evaluate the scalability of the proposed technique using synthetic and real application scenarios, as well as the security of the proposed technique.

A correction code for multiple cells upsets in memory devices for space applications

As the microelectronics technology continuously scales down, the probability of multiple cell upsets (MCUs) induced by radiation in memory devices increases. It is required a robust error correction code (ECC), that has also an area, energy-efficient silicon implementation, to protect electronic devices from MCUs. This article describes the conception, implementation, and evaluation of a new algorithm called CLC, for the detection and correction of multiple errors in memories devices by using extended Hamming and parity bits. The rates of detection and correction of CLC are compared to other correction codes, as well as their implementation cost. The results demonstrated that the CLC has high correction efficiency for MCUs aligned with low area, energy, and delay overhead than the other evaluated codes.

A fault prediction module for a fault tolerant NoC operation

Each new production technology of integrated circuit (IC) drives more transistors area reduction, implying smaller and denser circuits. This scenario allows integrating several Processing Elements (PEs) into the same IC with efficient communication architecture such as the scalable topologies of Network on Chip (NoC). However, these newer production technologies introduce more defects in various parts of the IC that have to be detected and well corrected to prevent malfunction of the IC. This work presents the Fault Prediction Module (FPM), which presents low area consumption and a power circuit based on thresholds enabling to detect link quality, i.e. operating properly, operating with fault tendency or with permanent fault. Additionally, we show how to tune the FPM threshold parameter aiming to use this circuit as a mechanism with comprehensive fault model. The set of experimental results shows the effectiveness of our proposal.

Evaluation of multiple bit upset tolerant codes for NoCs buffering

Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a communication architecture with high scalability and a high degree of parallelism, such as a Network-on-Chip (NoC). As the integration technology scales down, the probability of Multiple Cell Upsets (MCUs) increases. NoC buffers are exposed to MCUs induced by different sources. In this paper, we evaluate Error Correction Codes (ECCs) to protect NoC buffers from permanent MCUs. We guide our evaluation to measure the area and power overhead of each implementation of ECC, as well as their correction and detection rates. We conducted experiments varying buffer parameters (16 and 32-bits flit length) and three different protection codes. The results show that the costs of adding an ECC in each input buffer of the NoC are justified by the decrease of error occurrence for systems exposed to MCU events.

Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs

The latest technologies of integrated circuit manufacturing allow billions of transistors to be arranged on a single chip, enabling the chip to implement a complex parallel system, which requires a communications architecture that has high scalability and a high degree of parallelism, such as a Network-on-Chip (NoC). These technologies are very close to the physical limitations, which increases the faults in manufacturing and at runtime. Therefore, it is essential to provide a method for fault recovery that would enable the NoC to operate in the presence of faults and still ensure deadlock-free routing. The preprocessing of the most probable fault scenarios enables us to anticipate the calculation of deadlock-free routings, reducing the time that is necessary to interrupt the system during a fault occurrence. This work proposes a technique that employs the preprocessing of fault scenarios based on forecasting fault tendencies, which is performed with a fault threshold circuit operating in accordance with high-level software. We propose methods for dissimilarity analysis of scenarios based on cross-correlation measurements of link fault matrices. Experimental results employing RTL simulation with synthetic traffic prove the quality of the analytic metrics that are used to select the preprocessed scenarios. Furthermore, the experiments show the efficacy and efficiency of the proposed dissimilarity methods, quantifying the latency penalization when using the coverage scenarios approach.

An efficient, low-cost ECC approach for critical-application memories

Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy is required for its implementation, becoming a problem if applied in application where resources are scarce. This article presents the implementation and evaluation of the Matrix Region Section Code (MRSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. The experimental results measuring error coverage composed by detection and correction analysis, area, power and delay overheads have shown that MRSC is an excellent option to counteract with MCUs.

Efficient traffic balancing for NoC routing latency minimization

Modern technologies of integrated circuits allow billions of transistors arranged into a single chip, enabling to implement complex systems, which need a scalable and parallel communication architecture. Network-on-Chip (NoC) is a natural candidate to fulfill such communication requirements, providing high performance when the communication demands are balanced. This work proposes a new static balancing method that uses the applications traffic pattern for NoC latency reduction. This method allows the generation of a deterministic routing algorithm with simplistic implementation and low latency. Experimental results compare four balancing methods, showing the improvement of the proposed static balancing concerning the average NoC latency.

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs

Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide a fault recovery mechanism for NoC operation in the presence of faults. The preprocessing of the most probable fault scenarios and flits retransmission capability enable to anticipate the calculation of deadlock-free routings, reducing the time necessary to interrupt the system in a fault occurrence and maintaining links operating with retransmission capability. This work proposes a smart decisions mechanism for errors on NoC links, which is composed of a hardware part implemented into the links and routers, and a software part implemented inside an operating system kernel of each processor. The mechanism defines thresholds where is better to reconfigure the NoC or to retransmit flits with errors. Experimental results, with several NoC sizes and some error models, suggest when is better to reconfigure the NoC and when is better to maintain some links operating with eventual faults.

Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs

Newest processes of CMOS manufacturing allow integrating billions of transistors in a single chip. This huge integration enables to perform complex circuits, which require an energy efficient communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). However, these technologies are very close to physical limitations implying the susceptibility increase of faults on manufacture and at runtime. Therefore, it is essential to provide a method for efficient fault recovery, enabling the NoC operation even in the presence of faults on routers or links, and still ensure deadlock-free routing even for irregular topologies. A preprocessing approach of the most probable fault scenarios enables to anticipate the computation of deadlock-free routings, reducing the time necessary to interrupt the system operation in a fault event. This work describes a preprocessing technique of fault scenarios based on forecasting fault tendency, which employs a fault threshold circuit and a high-level software that identifies the most relevant fault scenarios. We propose methods for dissimilarity analysis of scenarios based on measurements of cross-correlation of link fault matrices. At runtime, the preprocessing technique employs analytic metrics of average distance routing and links load for fast search of sound fault scenarios. Finally, we use RTL simulation with synthetic traffic to prove the quality of our approach.

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.