César A. M. Marcon

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Complex applications implemented as systems on chip (SoC) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoC). Modeling applications involves capturing its computation and communication characteristics. Previously proposed communication weighted models (CWM) consider only the application communication aspects. This work proposes a communication dependence and computation model (CDCM) that can simultaneously consider both aspects of an application. It presents a solution to the problem of mapping applications on regular NoC while considering execution time and energy consumption. The use of CDCM is shown to provide estimated average reductions of 40% in execution time, and 20% in energy consumption, for current technologies.

Time and energy efficient mapping of embedded applications onto NoCs

This work analyzes the mapping of applications onto generic regular networks-on-chip (NoCs). Cores must be placed considering communication requirements, so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus potential contentions in the intercommunication of the cores. Experimental results for a suite of 22 benchmarks and various NoC sizes show that a 42% average reduction in the execution time of the mapped application can be obtained, together with a 21% average reduction in the total energy consumption for state-of-the-art technologies.

Comparison of network-on-chip mapping algorithms targeting low energy consumption

One relevant problem in current SoC design is the mapping of modules on a network-on-chip (NoC) targeting low energy consumption. In order to solve this mapping problem, several models are available to capture computation and communication characteristics of applications. The main goal of this article is to propose and compare algorithms for obtaining low energy mappings onto NoCs using a communication-weighted model (CWM). These include from exhaustive search to stochastic search methods and heuristic approaches, plus pertinent combinations. Two new heuristics are proposed, called largest communication first (LCF) and greedy incremental (GI). In addition, it describes algorithms that provide specially designed combinations of LCF with simulated annealing and tabu search. The use of LCF and combined approaches compared with pure stochastic algorithms provides average reductions above 98% in execution time, while keeping energy saving within at most 5% of the best results. Besides, the use of the heuristic GI alone provides average reductions in execution time above 90%, when compared with pure stochastic algorithms, and obtains better energy saving results than LCF and combined approaches for large NoCs.

Energy and latency evaluation of NoC topologies

Mapping applications onto different networks-on-chip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like latency and energy consumption. In this work, an algorithm devoted to evaluate different topologies is proposed. The evaluation starts with an application model called application communication pattern (ACP), which specifies tasks with the computation load and communication profile. ACP focuses on communication aspects and is an appropriate model to obtain mappings that comply with application requirements. ACP allows fast analysis over many NoC topologies, helping the system designer to evaluate the communication performance of a NoC-based system; this performance strongly depends on the placement of the cores, and it is computationally hard to find the optimal placement.

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

Networks-on-chip (NoCs) are communication architecture alternatives for complex systems-on-chip (SoCs) designs, due to their high scalability and bandwidth. In this paper, we consider a heterogeneous NoC as an alternative to match performance and energy requirements for dedicated applications. By employing an optimized mix of different routers, a heterogeneous network optimized for latency and energy consumption is achieved. A dedicated data structure, the application communication pattern (ACP), models the application, enabling the specification of the communication requirements among cores, together with their execution performance. ACP allows fast analysis, helping the system designer to evaluate the communication performance of a NoC-based system; this performance strongly depends on the placement of the cores, and it is computationally hard to find the optimal placement. An optimization algorithm mixes different router architectures

RTOS Scheduler Implementation in Hardware and Software for Real Time Applications

composing a heterogeneous NoC - and finds optimal placements for application cores. Therefore, a heterogeneous NoC can be achieved, which complies to the application requirements with minimum latency and energy, enabling one to obtain the Pareto curve relating latency and energy for a given application

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs

In order to enhance performance and improve predictability of the real time systems, implementing some critical operating system functionalities, like time management and task scheduling, in software and others in hardware is an interesting approach. Scheduling decision for real-time embedded software applications is an important problem in real-time operating system (RTOS) and has a great impact on system performance. In this paper, we evaluate the pros and cons of migrating RTOS scheduler implementation from software to hardware. We investigate three different RTOS scheduler implementation approaches: (i) implemented in software running in the same processor of the application tasks, (ii) implemented in software running in a co-processor, and (iii) implemented in hardware, while application tasks are running on a processor. We demonstrate the effectiveness of each approach by simulating and analyzing a set of benchmarks representing different embedded application classes

Evaluation of Algorithms for Low Energy Mapping onto NoCs

Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally provide a local view, which considers only the neighborhood of the mapping task. This work aims to evaluate the pros and cons of static and dynamic mapping solutions. Due to the global system view, it is expected that static mapping algorithms achieve superior performance (w.r.t. latency, congestion, energy consumption). As dynamic scenarios are a trend in present MPSoC designs, the cost of dynamic mapping algorithms must be known, and directions to improve the quality of such algorithms should be provided without increasing execution time. This quantitative comparison between static and dynamic mapping algorithms is the main contribution of this work.

Abstract RTOS modeling for embedded systems

Systems on chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping onto a NoC targeting low energy. To date, few works are available on design and evaluation of mapping algorithms. The main goal of this work is to propose some algorithms and evaluate its results and performance with regard to low energy NoC mappings. These include exhaustive and stochastic search methods and heuristic approaches, and some combinations. The use of combined approaches compared to pure stochastic algorithms provides average reductions above 98% in execution time, while keeping energy saving within at most 5% of the best results. In addition, one heuristic provided average reductions in execution time above 90% when compared to pure stochastic algorithms, and obtained better energy saving than combined approaches.

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation

Raising the abstraction level is widely seen as a solution to increase productivity, in order to handle the growing complexity of real-time embedded applications and the time-to-market pressures. In this context, the use of a real-time operating system (RTOS) becomes extremely important to the development of applications with real-time systems requirements. However, the use of a detailed RTOS at early design phases is a contra sense, and the existing system level description languages (SLDL) lack support for RTOS modeling at higher abstraction levels. In this paper, we introduce an abstract RTOS model, and a set of refinement steps that allows refining the abstract model to an implementation model at lower abstraction levels. This abstract RTOS model provides the main features available in a typical RTOS, permitting the designer to model parallel and concurrent behavior of real-time embedded applications at higher abstraction levels. We use SystemC language with some extensions to build the abstract RTOS model, allowing a quick evaluation of different scheduling algorithms and synchronization mechanisms at the early stage of system design. An experimental result with a telecom system that consists of fifty tasks with four priority levels shows the usefulness of this model.