Jason A. Trachewsky

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm2 of area in a digital 0.13 mum CMOS process of which 0.29 mm2 is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.

LDPC code set for mmWave communication

A low-density parity-check (LDPC) code set is presented that is specifically designed for multi-gigabit throughput wireless communication in the 60GHz band. The code set is structured to enable low power decoder and encoder implementation while providing excellent coding gain over a wide variety of channels.

A 2×2 MIMO baseband for high-throughput wireless local-area networking (802.11n)

This article consists of a collection of slides from the authors conference presentation on a 2X2 MIMO basedband system for high throughput wireless local area networking. Some of the specific topics discussed include: the demand for wireless LAN, 2000-2011; schemas of multipath channels; exploiting multipath processing for high rates and the impact on energy capacity planning; system architecture for MIMO-ODFM; system processing capabilities and performance summaries; the need for flexible transceivers; and block diagrams and system topologies.