Jason M. Kulick

Ultrawide Bandwidth Chip-to-Chip Interconnects for III-V MMICs

Ultrawide bandwidth coplanar waveguide interconnects between GaAs chips based on a novel fabrication process are demonstrated. Fabricated structures on 100 μm thick GaAs chips exhibited chip-to-chip insertion losses below 1 dB up to 110 GHz, and below 2.2 dB up to 220 GHz from on-wafer S-parameter measurements. A return loss larger than 10 dB from 100 MHz to 220 GHz was measured. The measured responses are consistent with numerical simulations, including the effects of excess solder at the chip-to-chip interface. Numerical simulations indicate that further improvements in performance, with insertion losses as low as 1.1 dB at 220 GHz, should be possible by minimizing the excess solder.

Scalable emitter array development for infrared scene projector systems

Several new technologies have been developed over recent years that make a fundamental change in the scene projection for infrared hardware in the loop test. Namely many of the innovations are in Read In Integrated Circuit (RIIC) architecture, which can lead to an operational and cost effective solution for producing large emitter arrays based on the assembly of smaller sub-arrays. Array sizes of 2048x2048 and larger are required to meet the high fidelity test needs of today’s modern infrared sensors. The Test Resource Management Center (TRMC) Test and Evaluation/Science and Technology (T and E/S and T) Program through the U.S. Army Program Executive Office for Simulation, Training and Instrumentations (PEO STRI) has contracted with SBIR and its partners to investigate integrating new technologies in order to achieve array sizes much larger than are available today. SBIR and its partners have undertaken several proof-of-concept experiments that provide the groundwork for producing a tiled emitter array. Herein we will report on the results of these experiments, including the demonstration of edge connections formed between different ICs with a gap of less than 10µm.

Heterogeneous microwave and millimeter-wave system integration using quilt packaging

Quilt Packaging (QP) is a direct chip-to-chip edge-interconnect technology that offers extremely low interconnect loss and can be implemented on a variety of substrates. We report here the experimental demonstration of heterogeneous integration between Si and GaAs substrates. Ultrawide-bandwidth Quilt Packaging coplanar waveguide interconnects between Si and GaAs chips are presented along with preliminary thermal shock data. Fabricated structures on ~100 μm thick Si and GaAs chips exhibited chip-to-chip insertion losses below 0.5 dB up to 170 GHz, and below 1 dB up to 220 GHz from on-chip S-parameter measurements. Simulated results on a heterogeneous Si-GaAs quilted chipset on scaled QP interconnect exhibited chip-to-chip insertion losses below 0.5 dB up to 300 GHz, and below 1.5 dB up to 750 GHz. Despite the coefficient of thermal expansion mismatch between Si and GaAs, the interconnects also exhibited no adverse effects from thermal shock testing through 1250 cycles.

High-Efficiency Oxide-Confined Ridge Waveguide Laser with Nearly Symmetric Output Beam

High-index-contrast InAlGaAs/AlGaAs ridge waveguide lasers exhibiting low threshold current and high efficiency are fabricated by a deep etch plus modified wet thermal oxidation process. A nearly-symmetric output beam is achieved for a 1.4mum wide aperture device

Thermal Cycling Study of Quilt Packaging

The continued progress of micro-electronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chip-packaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packaging® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawide-bandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quilt” of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.

FDTD modeling of chip-to-chip waveguide coupling via optical quilt packaging

We present Finite-Difference Time-Domain (FDTD) simulations to explore feasibility of chip-to-chip waveguide coupling via Optical Quilt Packaging (OQP). OQP is a newly proposed scheme for wide-bandwidth, highly-efficient waveguide coupling and is suitable for direct optical interconnect between semiconductor optical sources, optical waveguides, and detectors via waveguides. This approach leverages advances in quilt packaging (QP), an electronic packaging technique wherein contacts formed along the vertical faces are joined to form electrically-conductive and mechanically-stable chip-to-chip contacts. In OQP, waveguides of separate substrates are aligned with sub-micron accuracy by protruding lithographically-defined copper nodules on the side of a chip. With OQP, high efficiency chip-to-chip optical coupling can be achieved by aligning waveguides of separate chips with sub-micron accuracy and reducing chip-to-chip distance. We used MEEP (MIT Electromagnetic Equation Propagation) to investigate the feasibility of OQP by calculating the optical coupling loss between butt coupled waveguides. Transmission between a typical QCL ridge waveguide and a single-mode Ge-on-Si waveguide was calculated to exceed 65% when an interchip gap of 0.5 μm and to be no worse than 20% for a gap of less than 4 μm. These results compare favorably to conventional off-chip coupling. To further increase the coupling efficiency and reduce sensitivity to alignment, we used a horn-shaped Ge-on-Si waveguide and found a 13% increase in coupling efficiency when the horn is 1.5 times wider than the wavelength and 2 times longer than the wavelength. Also when the horizontal misalignment increases, coupling loss of the horn-shaped waveguide increases at a slower rate than a ridge waveguide.

Mid-Infrared Waveguide Array Inter-Chip Coupling Using Optical Quilt Packaging

A MEMS-based mid-infrared (MIR) chip-to-chip optical coupling technique, optical quilt packaging (OQP), is described. Numerical simulations are performed to predict performance and establish fabrication tolerances. The OQP fabrication process is described in detail and MIR inter-chip optical coupling between two waveguide arrays joined by OQP is characterized. The coupling loss between Ge-on-Si passive MIR waveguides is found to be ~ 4.1 dB, which is the lowest butt-coupling loss reported between two chips.

Demonstration: Quilt packaging for heterogeneous integration of CNN systems

A demonstration is presented at the 14th International Workshop on Cellular Nanoscale Networks and their Applications. The topic is the interchip interconnect technology known as Quilt Packaging™ (QP). QP offers many advantages for future, highly integrated CNN systems. The author will have demonstration materials on hand for inspection and discussion.