Jason Meiring

Fundamental investigation of negative tone development (NTD) for the 22nm node (and beyond)

In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental materials/process interaction perspective. Several key differences exist between a negative tone develop process and a traditional positive tone develop system. For example, the organic solvent dissolves the unexposed material, while the deprotected resist remains intact. This causes key differences in key patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity. We have carried out fundamental studies to understand these new interactions between developer and remaining resist with negative tone develop systems. We have characterized the dynamic dissolution behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent developers. We have also compared contrast curves, and a fundamental model of image collapse. In addition, we present first results on Optical Proximity Correction (OPC) modeling results of current Negative Tone Develop (NTD) resist/developer systems.

Demonstrating the benefits of source-mask optimization and enabling technologies through experiment and simulations

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability in illumination5-7 and have pushed the required optimization performance of mask design.8, 9 This paper will present recent experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,1, 6, 7 and we will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique (RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction, as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization with both source and mask variables jointly has been previously discussed.1-3 This paper will build on these results by demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

22-nm-node technology active-layer patterning for planar transistor devices

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.

Modeling polarization for hyper-NA lithography tools and masks

We present a comprehensive modeling study of polarization effects for the whole optical chain including exposure tool and mask, with strong emphasis on the impact of the Jones Matrix of the projection lens. First we start with the basic of polarization and then the polarization effect of each components of the optical chain will be discussed. Components investigated are source polarization, rigorous EMF effect, mask blank birefringence, pellicle effect and projection lens. We also focus on comparing the relative merits of different types of representation of Jones matrix of the projection lens and outlined ways to decompose the Jones Matrix. Methodologies such as Pauli matrix, PQM, Jones-Zernike expansion and IPS-Zernike expansion are among the ones investigated. The polarization impact on lithography and OPC on realistic 45nm and 32nm node process levels is discussed. Issues in OPC modeling with Jones Matrix is highlighted. Concerns regarding the standardization of the implementation of Jones Matrix in the lithography community are considered and a standard has been proposed and received wide acceptance. Last we discuss the challenge of using polarization and some novel ideas to deal with polarization in hyper NA era. Throughout the paper the resist component is not included so as to isolate the effect of resist from that of the other components.

22 nm technology node active layer patterning for planar transistor devices

As the semiconductor device size shrinks without concomitant increase of the numerical aperture (NA=1.35) or index of the immersion fluid from 32 nm technology node, 22 nm patterning technology presents challenges in resolution as well as process window. Therefore, aggressive Resolution Enhancement Technique (RET), Design for Manufacturability (DFM) and layer specific lithographic process development are strongly required. In order to achieve successful patterning, co-optimization of the design, RET and lithographic process becomes essential at the 22 nm technology node. In this paper, we demonstrate the patterning of the active layer for 22 nm planar transistor device and discuss achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D features simultaneously without sacrificing the cell size, while maintaining large process window. As the poly-gate pitch is tightened, the need for improved corner rounding performance is required inorder to ensure proper gate length across the entire gate width. Utilizing water immersion at NA=1.2 and 1.35, we will demonstrate patterning of the active layer in a 22 nm technology node SRAM of a bit-cell having a size of 0.1 μm2 and smaller while providing large process window for other features across the chip. It is shown that highly layer-specific and design-aware RET and lithographic process developments are critical for the success of 22 nm node technology.

Applicability of global source mask optimization to 22/20nm node and beyond

Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the source and mask, which yields improved lithographic performance. This paper will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and superior performance on two dimensional (2D) features. The benefits from only optimized source, only optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we leverage the benefits from intensively optimized masks to solve large array problems in memory use models (MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including both RETs and MUMs, in several critical layers during 22/20nm technology node development. Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during 22/20nm node development.

Statistical optimization of sampling plan and its relation to OPC model accuracy

In this paper, we seek a systematic strategy for creation of a wafer sampling plan and to determine the relationship between this plan and the OPC model accuracy. We start our study with the traditional error components analysis of wafer data. From this, we introduce our methodology of calculating the effective sample size based on each pattern and its error components. With all the error components separated, the confidence of the estimated mean can be calculated and, hence, an error bar can be added to each mean of the wafer data. This error bar is then used to determine which patterns are over-fitting and which patterns require an improved fit. We will present a method of providing an optimized and economical solution for wafer sampling. With this calculated error bar, the ultimate metric for OPC model accuracy will also be discussed.

Enabling reverse tone imaging for via levels using attenuated phase shift mask and source optimization

Printing small vias with tight pitches is becoming very challenging and consequently, different techniques are explored to achieve a robust and stable process. These techniques include reverse tone imaging (RTI) process, source optimization, mask transmission (attenuated Phase Shift Masks (attnPSM) versus binary thin OMOG masks), three-dimensional mask effects models, and SRAF printing models. Simulations of NILS, MEEF, DoF and process variability (PV) band width across a wide range of patterns are used to compare these different techniques in addition to the experimental process window. The results show that the most significant benefits can be gained by using attnPSM masks in conjunction with source optimization and RTI process. However, this improvement alone is not enough; every facet of the computational lithography and process must be finely tuned to produce sufficient imaging quality. As technology continues to shrink, Electromagnetic Field (EMF)-induced errors limit the scalability of this process and we will discuss the need for advanced techniques to suppress and correct for them.

The comparison of OPC performance and run time for dense versus sparse solutions

The lithographic processes and resolution enhancement techniques (RET) needed to achieve pattern fidelity are becoming more complicated as the required critical dimensions (CDs) shrink. For technology nodes with smaller devices and tolerances, more complex models and proximity corrections are needed and these significantly increase the computational requirements. New simulation techniques are required to address these computational challenges. The new simulation technique we focus on in this work is dense optical proximity correction (OPC). Sparse OPC tools typically require a laborious, manual and time consuming OPC optimization approach. In contrast, dense OPC uses pixel-based simulation that does not need as much manual setup. Dense OPC was introduced because sparse simulation methodology causes run times to explode as the pattern density increases, since the number of simulation sites in a given optical radius increases. In this work, we completed a comparison of the OPC modeling performance and run time for the dense and the sparse solutions. The analysis found the computational run time to be highly design dependant. The result should lead to the improvement of the quality and performance of the OPC solution and shed light on the pros and cons of using dense versus sparse solution. This will help OPC engineers to decide which solution to apply to their particular situation.