Jason N. Dale

Cell broadband engine architecture and its first implementation: a performance view

The Cell Broadband Engine™ (Cell/B.E.) processor is the first implementation of the Cell Broadband Engine Architecture (CBEA), developed jointly by Sony, Toshiba, and IBM. In addition to use of the Cell/B.E. processor in the Sony Computer Entertainment PLAYSTATION® 3 system, there is much interest in using it for workstations, media-rich electronics devices, and video and image processing systems. The Cell/B.E. processor includes one PowerPC® processor element (PPE) and eight synergistic processor elements (SPEs). The CBEA is designed to be well suited for a wide variety of programming models, and it allows for partitioning of work between the PPE and the eight SPEs. In this paper we show that the Cell/B.E. processor can outperform other modern processors by approximately an order of magnitude and by even more in some cases.

Software architecture and system validation of an open, unified model for accelerated multicore computing

For systems that use hardware accelerators to combine multicore and multiprocess technology with libraries and computational kernels, the drawbacks are the complexity of the programming model and the corresponding verification of the software and validation of the system performance capabilities. In this paper, we describe a software approach to utilizing the compute power of the Cell Broadband Engine® processor and a cluster composed of x86-64 and IBM PowerXCell™ 8i processors integrated within a single hybrid compute node. We review past approaches to provide motivation for our development of the Data Communication and Synchronization (DaCS) library and Accelerated Library Framework (ALF), which enable developers to create new applications and adapt existing applications to exploit hybrid computing platforms. We follow with examples of porting existing x86-64 processor-based applications to the hybrid cluster platform in order to demonstrate the capabilities of ALF and DaCS and discuss how one application was extended to become a stress and performance test for various system components. Finally, we present the applicability of this programming model, accelerator design, and test architecture to other system architectures, applications, and workload segments.