Timothy H. Heil

Architecture and Performance of the Hardware Accelerators in IBM’s PowerEN Processor

Computation at the edge of a datacenter has unique characteristics. It deals with streaming data from multiple sources, going to multiple destinations, often requiring repeated application of one or more of several standard algorithmic kernels. These kernels, related to encryption, compression, XML Parsing and regular expression searching on the data, demand a high data processing rate and power efficiency. This suggests the use of hardware acceleration for key functions. However, robust general purpose processing support is necessary to orchestrate the flow of data between accelerators, as well as perform tasks that are not suited to acceleration. Further, these accelerators must be tightly integrated with the general purpose computation in order to keep invocation overhead and latency low. The accelerators must be easy for software to use, and the system must be flexible enough to support evolving networking standards.In this article, we describe and evaluate the architecture of IBM’s PowerEN processor, with a focus on PowerEN’s architectural enhancements and its on-chip hardware accelerators.PowerEN unites the throughput of application-specific accelerators with the programmability of general purpose cores on a single coherent memory architecture. Hardware acceleration improves throughput by orders of magnitude in some cases compared to equivalent computation on the general purpose cores. By offloading work to the accelerators, general purpose cores are freed to simultaneously work on computation less suited to acceleration.

Performance and power evaluation of an in-line accelerator

In this paper we evaluate the performance and power of a processor-attached in-line accelerator. The accelerator provides high-performance SIMD computing and power efficiency by means of a very large register file and a set of vector multimedia extensions based on IBMs PowerPC VMX. Our experiments show significant performance improvements and power reduction, compared to a baseline vector execution unit, mainly due to the drastic decrease of memory accesses caused by the software-managed locality of the very large register file. Total execution time is, on average, reduced by 61%, while consuming 55% less energy.