Jaume Roig

Analytical Switching Loss Model for Superjunction MOSFET With Capacitive Nonlinearities and Displacement Currents for DC–DC Power Converters

A new analytical model is presented in this study to predict power losses and waveforms of high-voltage silicon superjunction MOSFET during hard-switching operation. This model depends on datasheet parameters of the semiconductors, as well as the parasitics obtained from the printed circuit board characterization. It is important to note that it also includes original features accounting for strong capacitive nonlinearities and displacement currents. Moreover, these features demand unusual extraction of electrical characteristics from regular datasheets. A detailed analysis on how to obtain this electrical characteristic is included in this study. Finally, the high accuracy of the model is validated with experimental measurements in a double-pulse buck converter setup by using commercial SJ MOSFET, as well as advanced device prototypes under development.

Internal self-damping optimization in trench power FETs for high-frequency conversion

The impact of the shield resistance (Rsh) on the waveform ringing and system efficiency is assessed in this work for 30V trench power FETs with shielded-gate (TP-FETs). Two different approaches, named distributed and local Rsh, are extensively investigated by experimental and numerical simulation tools. A layout distributed Rsh emerges as the ultimate solution to maximize the self-damping without penalization on the switching power losses or the product cost. The practical implementation of a TP-FET with distributed Rsh in a 12V-to-1.2V buck converter results in one of the best tradeoffs ever reported between overvoltage (<;3.5V) and peak efficiency (~88%) when operating at 1.3MHz.

Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)

The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).

Enhancing the robustness of a multiple floating field-limiting ring termination by introducing a buffer layer

A planar multiple floating field-limiting ring structure, designed for above 600V blocking capability, is analyzed in this work. We have proven by simulation and experiment that adding a well designed buffer layer in the epi-substrate region counteracts on the drop in electric field which is due to the space charge limited current and as such the buffer enhances the robustness towards reverse voltage biasing.

A high-speed silicon FET for efficient DC-DC power conversion

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

Thermal resistance assessment in multi-trenched power devices

Abstract For the first time the thermal resistance ( R th ) of Multi-Trenched (MT) power devices is evaluated and compared with their Deep Trench Isolation flanked (DTI-flanked) and bulk counterparts. The R th extraction is carried out by adapted test structures based on the four-point heater/sensor method. Additional TCAD simulation supports the experimental stationary values and proves that dynamic heating can limit the MT power devices energy capability.

Theoretical analysis of XtreMOS ™ power transistors

This work provides a new theoretical approach addressed to the XtreMOSTM and equivalent structures. An analytical sRonxBVdss model is provided to demonstrate the superior electrical performance of XtreMOSTM structure in the domain of the high power MOSFETs at medium voltage capability (50-200 V). Moreover, geometrical and technological parameters can be easily optimized by means of simple expressions. In order to support and validate the theoretical approach, numerical simulation and experimental data are included.

Solutions to improve flatness of Id-Vd curves of rugged nLDMOS

This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.

Accumulation region length impact on 0.18µm CMOS fully-compatible lateral power MOSFETs with Shallow Trench Isolation

N-type lateral power MOSFETs (nLDMOS) with Shallow Trench Isolation (STI) and voltage capability between 12 and 22V are analyzed in this work by experiment and TCAD simulation. A 0.18um CMOS technology is used to integrate nLDMOS devices without additional mask or process. Differently from previous works, the paramount impact of the accumulation region length (Lacc) on the Safe Operating Area (SOA), gate-to-drain charge (Qgd) and Hot Carrier (HC) degradation is deeply explored to optimize the device electrical performance and reliability.

Energy limits for unclamped inductive switching in high-voltage planar and SuperJunction power MOSFETs

In this work the maximum UIS energy capability (Eas) for High-Voltage (600V-900V) Planar and SuperJunction (SJ) power MOSFETs is analyzed through experiment, TCAD simulation and analytical modeling. A new theoretical approach considering a buried heat source is presented to accurately predict Eas values in a wide range of voltage capability and load inductor values.