Javier Carretero

Low Vccmin fault-tolerant cache with highly predictable performance

Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent excessive degradation and keep power demand within reasonable limits. Unfortunately, low Vcc operation exacerbates the effect of variations and decreases noise and stability margins, increasing the likelihood of errors in SRAM memories such as caches. Those errors translate into performance loss and performance variation across different cores, which is especially undesirable in a multi-core processor. This paper presents (i) a novel scheme to tolerate high faulty bit rates in caches by disabling only faulty subblocks, (ii) a dynamic address remapping scheme to reduce performance variation across different cores, which is key for performance predictability, and (iii) a comparison with state-of-the-art techniques for faulty bit tolerance in caches. Results for some typical first level data cache configurations show 15% average performance increase and standard deviation reduction from 3.13% down to 0.55% when compared to cache line disabling schemes.

Immediate mode scheduling in grid systems

Computational Grids (CGs) are nowadays successfully responding to increasing needs for high computation power. A key issue in CGs is the scheduling, which demands for efficient methods. In this work, we consider the scheduling problem in immediate mode, in which jobs are allocated as soon as they arrive in the system. This type of scheduling arises in many grid-based applications, especially, in real-time applications. We have implemented five immediate scheduling methods and have measured their performance with respect to four parameters: makespan, flowtime, resource utilisation and matching proximity by using a simulation benchmark for heterogeneous distributed systems. The computational results showed the performance of the immediate scheduling methods and allowed us to evaluate the advantages of these methods if we knew in advance certain grid characteristics (consistency of computing, heterogeneity of jobs and resources). The usefulness of the presented methods in web and grid scheduling services is also discussed.

REQUIREMENTS FOR AN EVENT-BASED SIMULATION PACKAGE FOR GRID SYSTEMS

In this paper we present a study on the requirements for the design and implementation of simulation packages for Grid systems. Grids are emerging as new distributed computing systems whose main objective is to manage and allocate geographically distributed computing resources to applications and users in an efficient and transparent manner. Grid systems are at present very difficult and complex to use for experimental studies of large-scale distributed applications. Although the field of simulation of distributed computing systems is mature, recent developments in large-scale distributed systems are raising needs not present in the simulation of the traditional distributed systems. Motivated by this, we present in this work a set of basic requirements that any simulation package for Grid computing should offer. This set of functionalities is obtained after a careful review of most important existing Grid simulation packages and includes new requirements not considered in such simulation packages. Based on the identified set of requirements, a Grid simulator is developed and exemplified for the Grid scheduling problem.

Design and evaluation of tabu search method for job scheduling in distributed environments

The efficient allocation of jobs to grid resources is indispensable for high performance grid-based applications. The scheduling problem is computationally hard even when there are no dependencies among jobs. Thus, we present in this paper a new tabu search (TS) algorithm for the problem of batch job scheduling on computational grids. We consider the job scheduling as a bi-objective optimization problem consisting of the minimization of the makespan and flowtime. The bi-objectivity is tackled through a hierarchic approach in which makespan is considered a primary objective and flowtime a secondary one. An extensive experimental study has been first conducted in order to fine-tune the parameters of our TS algorithm. Then, our tuned TS is compared versus two well known TS algorithms in the literature (one of them is hybridized with an ant colony optimization algorithm) for the problem. The computational results show that our TS implementation clearly outperforms the compared algorithms. Finally, we evaluated the performance of our TS algorithm on a new set of instances that better fits with the concept of computational grid. These instances are composed of a higher number of -heterogeneous- machines (up to 256) and emulate the dynamic behavior of these systems.

End-to-end register data-flow continuous self-test

While Moores Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes, there is a lack of cost-effective mechanisms for control logic. This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. The structures protected include the issue queue logic and the data associated (i.e., tags and control signals), input multiplexors, rename data, replay logic, register free-list and release logic, and register file logic. Our results show a coverage around 90 percent for the targeted structures with a cost in power and area of about four percent, and without impact in performance.

On-Line Failure Detection and Confinement in Caches

Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing techniques to cope with hard errors in the field. Similarly, those techniques are needed for detecting soft errors in logic, whose error rate is expected to raise in future technologies. Cache memories, which occupy most of the area of the chip, are typically protected with parity or ECC, but most of the wires as well as some combinational blocks remain unprotected against both soft and hard errors. This paper presents a set of techniques to detect and confine hard and soft errors in cache memories in combination with parity/ECC at very low cost. By means of hard signatures in data rows and error tracking, faults can be detected, classified properly and confined for hardware reconfiguration.

Performance of sludge treatment wetlands using different plant species and porous media.

The aim of this study was to evaluate the dewatering and mineralisation efficiency of three sludge treatment wetlands (STW) configurations differing on plant species (Phragmites australis and Typha sp.) and filter medium (gravel and wood shavings). Sludge dewatering and mineralisation were monitored in three pilots STW for 2 years. The sludge volume was reduced by 80% in all configurations tested, the total solids (TS) increased to 16-24% TS and the volatile solids (VS) decreased to 50% VS/TS. After a resting period of three months the biosolids showed a high stabilisation (dynamic respiration index around 0.26-0.70 mgO(2)/gVS h), caused no phytotoxicity (germination index >100%), and had low heavy metals and pathogens concentrations (E. coli<240 MNP/g; absence of Salmonella). The lack of statistical significance (p>0.05) between the results obtained from the different STW configurations suggests that STW may be either planted with P. australis or Typha sp., and that wood shavings may replace gravel as filter medium.

Hardware/software-based diagnosis of load-store queues using expandable activity logs

The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors.

On-line Failure Detection in Memory Order Buffers

Technology scaling leads to burn-in phase out and higher post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors respectively. As a consequence, current reliability qualification methods will likely be infeasible. Microarchitecture knowledge of application runtime behavior offers a possibility to have low-cost continuous online testing techniques to cope with hard errors in the field. Whereas data can be protected with redundancy (like parity or ECC), there is a lack of mechanisms for control logic. This paper proposes a microarchitectural approach for validating that the memory order buffer logic works correctly.

Reliability and economic feasibility of online monitoring of constructed wetlands performance

AbstractThis study aimed at determining the reliability and feasibility of constructed wetlands (CWs) performance evaluation by online monitoring. Redox potential (EH), turbidity and ammonium (NH4) were continuously monitored for one year by means of online sensors in a pilot plant based on horizontal sub-surface flow constructed wetlands (HSSF CWs). Results were compared with conventional laboratory analyses. Online measures and laboratory analyses showed good agreement for NH4 (r = 0.84, p < 0.01). A significant correlation was also found for: online turbidity vs. Total suspended solids (TSS) (r = 0.85, p < 0.01); online turbidity vs. Biochemical oxygen demand (BOD) (r = 0.88; p < 0.01) and EH vs. BOD (r = −0.62; p < 0.01). Results suggested that in full-scale CWs, continuous monitoring of turbidity, EH and NH4 would help to both daily monitoring and improvement of CWs performance. A general overview about economic aspects suggested that, continuous monitoring of wastewater quality could be technically ...