Jawad Khan

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

Present day technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. The latest FPGAs can support only about 10 million gates to accomodate all logic and the associated routing. In order to implement a competitive NoC architecture in FP-GAs, the area occupied by the network should be kept to a minimum. This ensures that the maximum area can be utilized by the logic while maintaining the performance of the router network. Reducing area also reduces the power consumption. In this paper, we implement a parallel router which can support five simultaneous routing requests at the same time with an area overhead of only 352 Xilinx Virtex-II Pro FPGA slices (2. 57% of XC2VP30). We introduce optimizations in XY routing and decoding logic thereby gaining in area and performance. The header overhead is 8 bits per packet and the packet size can vary between 16 and 128 bits. We also implement a 3 x 3 mesh network with a total area overhead of 28% leaving 72% of the area available for the logic in a Virtex-II Pro XC2VP30 device. We characterize the router and several mesh networks for power and performance parameters.

An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms

We consider battery powered portable systems which either have field programmable gate arrays (FPGA) or voltage and frequency scalable processors as their main processing element. An application is modeled in the form of a precedence task graph at a coarse level of granularity. We assume that, for each task in the task graph, several unique design-points are available which correspond to different hardware implementations for FPGAs and different voltage-frequency combinations for processors. It is assumed that performance and total power consumption estimates for each design-point are available for any given portable platform, including the power usage of peripheral components, such as memory and display. We present an iterative heuristic algorithm which finds a sequence of tasks along with an appropriate design-point for each task, such that a deadline is met and the amount of battery energy used is as small as possible. A detailed illustrative example, along with a case study of a real-world application of a robotic arm controller which demonstrates the usefulness of our algorithm, is also presented.

Energy management for battery-powered reconfigurable computing platforms

We define portable reconfigurable computing platforms as those which have some form of configurable logic coupled with other on-chip or off-chip processing units such as soft processors, embedded processors, and voltage-scalable processors. In the first part of this paper, we present and test a unique methodology where we dynamically change the active area of a field programmable gate array (FPGA) to vary the battery usage and lifetime of the system, by running it on several different taskgraph structures and report an average of 14% and as high as 21%, less battery capacity used, as compared to nonoptimal execution. In the second part of this paper, we integrate the above methodology with more traditional voltage and frequency scaling techniques for portable systems and present a heuristic iterative algorithm for single and multiple processing units. The iterative heuristic algorithm finds a sequence of tasks along with an appropriate design point (implementation option) for each task, such that a deadline is met and the amount of battery energy used is as small as possible. We have used several real-world benchmarks to test the effectiveness of this methodology and we will present the results.

iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications

The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed for real time, in-field image processing applications. IPACE-V1 has ample memory and the capability of full or partial reconfiguration without the need of a host computer. This paper describes the architecture of the hardware board along with the software design environment. We shall also discuss a real-time background elimination application for video images implemented on iPACE-V1.

An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms

In this paper we present a simple yet efficient methodology for battery-aware task execution on FPGAs in portable Reconfigurable Computing (RC) platforms. We divide the reconfigurable area on an FPGA into several fixed reconfigurable slots called Configurable Tiles. We then schedule real-time tasks onto these tiles. Various schedules using different number of tiles are calculated off-line. These schedules along with their execution times are then sent to a run-time scheduler which dynamically decides, which schedule is the most battery efficient. By varying the number of tiles used for scheduling tasks, we can vary the battery usage and lifetime. We tested the methodology by running it on several different task graph structures and sizes, and report an average of 14% and as high as 21%, less battery capacity used, as compared to non-optimal execution. Finally, we present a case study where we implement a real-time face recognition algorithm on the iPACE-V1 [6] platform using the proposed methodology and observed 1.3 to 3.3 times improvement in battery life-time.

Energy management in battery-powered sensor networks with reconfigurable computing nodes

In this work we have investigated the benefits of using reconfigurable computing (RC) nodes in sensor networks. We assumed that several sensor nodes are deployed randomly in a field, to form a sensor network and each sensor in the network sends its data in the form of packets to a single energy-rich sink node. We also assumed that each sensor node has reconfigurable fabric which can be configured by downloading a bitstream. In contrast to the contemporary work in energy management for sensor networks, we use an accurate analytical battery model to simulate the battery consumption of each node in the network. We have written several simulation models to study various sensor network parameters when the underlying nodes are adaptive in nature instead of traditional, non-adaptive processor based, fixed implementation. As the remaining battery-capacity of our RC based node decreases, it changes its behavior by reconfiguring itself to lower powered implementations successively, thereby extending the sensor network lifetime as a whole. Our results indicate that the network life is increased by up to five times and the number of packets generated by the sensor nodes and received at the sink node more than quadrupled for RC based nodes when compared to fixed processor based node implementation.