Manish Handa

An efficient algorithm for finding empty space for online FPGA placement

A fast and efficient algorithm for finding empty area is necessary for online placement, task relocation and defragmentation on a partially reconfigurable FPGA. We present an algorithm that finds empty area as a list of overlapping maximal rectangles. Using an innovative representation of the FPGA, we are able to predict possible locations of the maximal empty rectangles. Worst-case time complexity of our algorithm is O(xy) where x is the number of columns, y is the number of rows and x.y is the total number of cells on the FPGA. Experiments show that, in practice, our algorithm needs to scan less than 15% of the FPGA cells to make a list of all maximal empty rectangles.

An Integrated Online Scheduling and Placement Methodology

Dynamic task scheduling and online placement are two of the main responsibilities of an operating system for reconfigurable platforms. Since these operations are performed during run-time of the applications, these are overheads on the execution time. There is a need to find fast and efficient algorithms for task placement and scheduling. We propose an integrated online scheduling and placement methodology. We maintain empty area as a list of maximal empty rectangles which allows us to explore solution space efficiently. We defer scheduling decisions until it is absolutely necessary to accommodate dynamically changing task priorities. We propose task queue management data-structures for in-order and out-of-order task scheduling strategies. One of our queuing strategies guarantees the shortest execution time for in-order task execution and the other strategy results in better FPGA area utilization for out-of-order task execution. We provide experimental evidence of improvement our methodology yields over the previous approaches.

A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement

In this paper, we present a fast algorithm for finding empty area on the FPGA surface with some rectangular tasks placed on it. We use a staircase data structure to report the empty area in the form of a list of maximal empty rectangles. We model the FPGA surface using an innovative encoding scheme that improves runtime and reduces memory requirement of our algorithm. Worst-case time complexity of our algorithm is O(xy) where x is number of columns, y is number of rows, and x.y is the total number of cells on the FPGA.

iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications

The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed for real time, in-field image processing applications. IPACE-V1 has ample memory and the capability of full or partial reconfiguration without the need of a host computer. This paper describes the architecture of the hardware board along with the software design environment. We shall also discuss a real-time background elimination application for video images implemented on iPACE-V1.

A fast macro based compilation methodology for partially reconfigurable FPGA designs

In this paper, we propose a methodology for automated mapping of a design onto a partially reconfigurable device. We generate partial bitstream files from behavioral description of the task, that are used to reconfigure the device dynamically. The novelty of this research lies in the application of a macro based synthesis approach that allows elimination of both logic synthesis and technology mapping phases from the synthesis flow. Our methodology provides a significant reduction in compilation time compared to commercial tools.

Hardware assisted two dimensional ultra fast placement

Summary form only given. Placement time is an overhead on the application execution time in an online placement system. In a partially reconfigurable system, the inherent parallelism of the reconfigurable hardware can be explored to speed up the placement process. We present three different architectures for two dimensional online placement. Each architecture makes different trade-offs between area usage, memory requirement and execution time. These architectures are capable of achieving very fast placement while using a very small number of hardware resources.

Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs

Dynamically reconfigurable devices allow run-time reconfiguration to permit execution of incoming tasks or task fragments. One of the important issues in run-time reconfiguration is the fragmentation of the device area as the reconfigurable blocks are allocated and released when tasks are placed, executed and deleted. Due to those scattered, unused resources, an incoming application may not be placeable or routable. A cluster-based reconfigurable FPGA architecture is proposed to alleviate this difficulty. We present an assessment of the proposed architecture. We develop a fast evaluation tool to simulate on-line placement and routing effects on a run-time reconfigurable platform. The simulation results show the efficiency of the proposed architecture in relieving the fragmentation problem at the price of a modest increase in the number of switches.