Jay Im

Thermo-mechanical reliability of 3-D ICs containing through silicon vias

In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses in silicon decrease as a function of distance from an isolated TSV and increase with the TSV diameter. Additional simulation suggested that hybrid TSV structures can significantly reduce the thermal stresses. An analytical stress solution was introduced to deduce the stress distribution around an isolated TSV, which was further developed to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. We calculated the crack driving force in TSV lines under a thermal load. The effects of TSV diameter, pitch size, and the line configuration on crack driving force were investigated.

Thermal stress induced delamination of through silicon vias in 3-D interconnects

In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element analysis (FEA) was used to evaluate the thermal stresses and the driving force of TSV delamaination. Then, the modeling results were validated by analytical solutions of the crack driving force deduced for a long crack at the steady state. Both results were found to be in good agreement at the steady state and together they suggested a fracture mechanism to account for the TSV delamination observed. The analytical solution further provided a basic framework for studying the impact of materials, process and structural design on reliability of the TSV structure. In particular, we found that reducing the TSV diameter yields a definite advantage in lowering the crack driving force. In addition, annular TSVs and an overlaying metal pad on a TSV can reduce the crack driving force for delamination during thermal cycling. Finally, the metallization effect was investigated for four TSV materials: copper, aluminum, nickel, and tungsten. Tungsten was found to have the smallest crack driving force due to the least thermal mismatch with the surrounding silicon. The reliability implication was discussed.

Electromigration enhanced intermetallic growth and void formation in Pb-free solder joints

A kinetic analysis was formulated for electromigration enhanced intermetallic evolution of a Cu–Sn diffusion couple in the Sn-based Pb-free solder joints with Cu under bump metallurgy. The simulated diffusion couple comprised the two terminal phases, Cu and Sn, as well as the two intermetallic phases, Cu3Sn and Cu6Sn5, formed between them. The diffusion and electromigration parameters were obtained by solving the inverse problem of the electromigration enhanced intermetallic growth, and they were compatible with the literature values. Finite difference method was applied to the whole simulated domain to solve for the mass transport kinetics within the intermetallic phases and across each interface of interest. Simulation showed that, when electromigration effect was absent (zero current), intermetallic growth followed a parabolic law, suggesting a diffusion controlled mechanism for thermal aging. However, under significant current stressing (4×104A∕cm2), the growth of the dominant intermetallic Cu6Sn5 cle...

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

Through-silicon via is a critical element for three-dimensional (3D) integration of devices in multilevel stack structures. Thermally induced stresses in through-silicon vias (TSVs) have raised serious concerns over mechanical and electrical reliability in 3D technology. An experimental technique is presented to characterize thermal stresses in TSVs during thermal cycling based on curvature measurements of bending beam specimens. Focused ion beam and electron backscattering diffraction analyses reveal significant grain growth in copper vias, which is correlated with stress relaxation during the first cycle. Finite element analysis is performed to determine the stress distribution and the effect of localized plasticity and to account for TSV extrusion observed during annealing.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects

In this paper, we demonstrated the plasticity mechanism for copper (Cu) extrusion in through-silicon via structures under thermal cycling. The local plasticity was directly observed by synchrotron x-ray micro-diffraction near the top of the via with the amount increasing with the peak temperature. The Cu extrusion was confirmed by Atomic Force Microscopy (AFM) measurements and found to be consistent with the observed Cu plasticity behavior. A simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface. The model predictions were able to account for the via extrusions observed in two types of experiments, with one representing a nearly free sliding interface and the other a strongly bonded interface. Interestingly, the AFM extrusion profiles seemed to contour with the local grain structures near the top of the via, suggesting that the grain structure not only affects the yield strength of the Cu and thus its plasticity but could also be important in controlling the pop-up behavior and the statistics for a large ensemble of vias.

Thermomechanical reliability of through-silicon vias in 3D interconnects

This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p- and n- channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up mechanism of TSV with a ‘nail head’. We first analyze the three-dimensional distribution of the thermal stresses near the TSV and the wafer surface. The stress characteristics are inherently 3D in nature with the near-surface stress distributions distinctly different from the 2D solution. The energy release rate for interfacial delamination of TSV is evaluated under both cooling and heating conditions, using an analytical solution for a steady-state crack growth as an upper bound and numerical solutions by finite element analysis (FEA) for more detailed calculations. Based on these results, we examine the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n- channel MOSFET devices, including the study of the effect of TSV scaling on the keep-out zone for MOSFET devices. This is followed by analyzing the energy release rate for interfacial delamiantion for a fully filled TSV and the potential mechanisms for TSV pop-up due to interfacial fracture.

Effect of intermetallic formation on electromigration reliability of TSV-microbump joints in 3D interconnect

In this study, electromigration (EM) reliability of TSV-microbump (μ-bump) joints was investigated. Sn-based μ-bumps with three different schemes of metallization were tested under current stressing at elevated temperatures. EM-stressed μ-bumps, together with thermal anneal-only μ-bumps and as-received controls, were cross-sectioned and characterized using scanning electron microscope (SEM), energy dispersed x-ray (EDX) and focused ion beam (FIB). Intermetallic compound (IMC) growth kinetics under EM for the three types of metallization were obtained, and compared with those subjected to thermal annealing only. Results showed good EM performance of the TSV μ-bump joints, indicating that IMC formation plays an important role in improving the EM reliability of μ-bump joints. However, non-EM related voids were observed in the μ-bumps, and the voiding mechanisms were discussed.

Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model With Cohesive Zone

An analytical approach to predict initiation and growth of interfacial delamination in the through-silicon via structure is developed by combining a cohesive zone model with a shear-lag model. Two critical temperatures are predicted for damage initiation and fracture initiation, respectively. It is found that via extrusion significantly increases beyond the second critical temperature. The dependence of the critical temperatures on the material/interfacial properties, as well as the via size (diameter and height), is discussed. In parallel with the analytical approach, finite-element models with cohesive interface elements are employed to numerically simulate the initiation and the progression of interfacial delamination. The numerical results are in good agreement with the analytical solution, and both are qualitatively consistent with reported experimental findings by others.

Effects of cap layer and grain structure on electromigration reliability of Cu/low-k interconnects for 45 nm technology node

The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40x lifetime improvement with a small lifetime variation (σ=0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the M2 level for both with and without the CoWP cap. The EM results showed that, for both caps, the Cu lines with the large grain structure had a longer EM lifetime compared with the small grain structure, and the EM enhancement of the metal cap was reduced for the small grain structure. Failure analysis revealed two failure modes for the SiCN cap, with void formation either at the via corner or in the trench away from the via; on the contrary, voids mostly formed several microns away from the via for the large grain CoWP cap. The difference in voiding locations for the two caps was attributed to the different interfacial mass transport rate. Implications of scaling effect on EM reliability were also discussed.