Suk-Kyu Ryu

Thermo-mechanical reliability of 3-D ICs containing through silicon vias

In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses in silicon decrease as a function of distance from an isolated TSV and increase with the TSV diameter. Additional simulation suggested that hybrid TSV structures can significantly reduce the thermal stresses. An analytical stress solution was introduced to deduce the stress distribution around an isolated TSV, which was further developed to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. We calculated the crack driving force in TSV lines under a thermal load. The effects of TSV diameter, pitch size, and the line configuration on crack driving force were investigated.

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n- and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.

Thermal stress induced delamination of through silicon vias in 3-D interconnects

In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element analysis (FEA) was used to evaluate the thermal stresses and the driving force of TSV delamaination. Then, the modeling results were validated by analytical solutions of the crack driving force deduced for a long crack at the steady state. Both results were found to be in good agreement at the steady state and together they suggested a fracture mechanism to account for the TSV delamination observed. The analytical solution further provided a basic framework for studying the impact of materials, process and structural design on reliability of the TSV structure. In particular, we found that reducing the TSV diameter yields a definite advantage in lowering the crack driving force. In addition, annular TSVs and an overlaying metal pad on a TSV can reduce the crack driving force for delamination during thermal cycling. Finally, the metallization effect was investigated for four TSV materials: copper, aluminum, nickel, and tungsten. Tungsten was found to have the smallest crack driving force due to the least thermal mismatch with the surrounding silicon. The reliability implication was discussed.

Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique

Through-silicon via is a critical element for three-dimensional (3D) integration of devices in multilevel stack structures. Thermally induced stresses in through-silicon vias (TSVs) have raised serious concerns over mechanical and electrical reliability in 3D technology. An experimental technique is presented to characterize thermal stresses in TSVs during thermal cycling based on curvature measurements of bending beam specimens. Focused ion beam and electron backscattering diffraction analyses reveal significant grain growth in copper vias, which is correlated with stress relaxation during the first cycle. Finite element analysis is performed to determine the stress distribution and the effect of localized plasticity and to account for TSV extrusion observed during annealing.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

Thermal Stresses Analysis Of 3-D Interconnect

In 3‐D interconnect structures, process‐induced thermal stresses around through silicon vias (TSVs) raise serious reliability issues such as silicon cracking and performance degradation of devices. In this study, the thermo‐mechanical reliability of 3‐D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. The thermal stress in silicon was found to decrease as a function of distance from an isolated TSV but increase with the TSV diameter. Additional simulation results demonstrated that hybrid TSV structures can significantly reduce thermal stresses. An analytical solution was introduced to deduce the stress distribution around an isolated TSV, which was applied to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. The stress interaction is directional dependent, thus the TSV array configuration can be optimized to improve the keep‐away‐zone design for stress‐sensitive devices.

Temperature-dependent thermal stress determination for through-silicon-vias (TSVs) by combining bending beam technique with finite element analysis

In this paper, temperature-dependent thermal stresses in Cu TSVs are measured by combining the bending beam experiment with a finite element analysis (FEA). The bending beam technique measures the averaged bending curvature induced by the thermal expansion of a periodic annular Cu TSV array. The structural complexity of the blind annular TSV necessitated the use of FEA to derive the TSV-induced thermal stresses which accounts for the beam bending during thermal cycles. The FEA simulations established linear relationships between bending curvature and stress components in TSVs. Such linear relationships were used to extract independent stress components from the bending beam measurements. The results provided an understanding to the temperature-dependent stress characteristics in TSVs.

Impact of Process Induced Stresses and Chip-Packaging Interaction on Reliability of Air-gap Interconnects

The mechanical stability of air-gap interconnect structures during thermal processing and under chip packaging interaction (CPI) were investigated using 3D multilevel finite element analysis (FEA) models. Low k cap delamination from the Cu barrier during thermal processing, channel cracking of the bridging cap and dielectric overlayers, and interface delamination under packaging were identified as the main concerns of mechanical stability and reliability for air-gap implementation. Simulation results revealed that the delamination driving force depends very much on the gap width to cap thickness ratio, the channel cracking issue in the dielectric overlayers can be managed in the presence of constraints from adjacent Cu wires, and the introduction of air-gaps significantly increases the interfacial delamination probability under the outermost solder bumps.

Impact of material and microstructure on thermal stresses and reliability of through-silicon via (TSV) structures

Thermal stresses and microstructures of two TSV structures with different fabrication conditions have been investigated using the precision wafer curvature and synchrotron x-ray microdiffraction methods, providing the first direct observation of local plasticity in the TSVs. Results from this study show that the electroplating chemistry directly affects the Cu microstructure, which in turn controls stress relaxation and build-up of the residual stress during thermal cycling. The implications on via extrusion and device keep-out zone (KOZ) are discussed.

Interfacial Delamination Between Through Silicon Vias (TSVs) and Silicon Matrix

Recently, three-dimensional (3-D) integration with through silicon vias (TSVs) has emerged as an effective solution for interconnect structures beyond the 32-nm technology node in microelectronics. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in 3-D interconnects. This paper examines the thermal stress-induced delamination between through silicon via (TSV) and the silicon matrix. First, the driving force for TSV delamination was derived for a long crack at the steady state, and then the analytical solutions were validated using finite element analysis (FEA). The analytical solutions and simulation results were found to be in good agreement at the steady state, and together they suggested a fracture mechanism to account for the TSV delamination observed. The analytical solution further provided a basic framework for studying the impact of materials, process and structural design on reliability of the TSV structure. In particular, we found that reducing the thermal mismatch and TSV diameter yield definite advantages in lowering the crack driving force for TSV delamination. Such driving force can also be controlled by introducing an annular metal filling or a dielectric liner between TSV and the Si matrix. Finally, the TSV protrusion phenomenon during thermal cycles was investigated. The interfacial delamination was found to initiate during a cooling process and to develop under a subsequent heating process, causing TSVs to protrude from the silicon matrix after repeated thermal cycles.Copyright