Changhui Hu

A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization

A fully-integrated, 3-5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Transmitter pre-emphasis equalization is utilized to mitigate the effect of multipath on bit-error rate (BER). Occupying 2 mm2 die area, the transceiver achieves a data rate of 500 Mbps, energy efficiency of 0.18 nj/b at 500 Mbps, and a RX raw BER of <; 10-3 across a distance of 10 cm at 125 Mbps. In a real multipath environment, BER improves by 2.35× after equalization of the first multipath reflection.

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges

This article advocates the use of short-range wireless communication inside a computing chassis. Ultrawideband links make it possible to design a within-chassis wireless interconnect. In contrast to conventional, fixed, wireline connections between chips, wireless communications offer certain unique advantages, as the authors explain.

A Near-Threshold, 0.16 nJ/b OOK-Transmitter With 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service

A 0.16 nJ/b MICS transmitter and 0.18 nJ/b super-regenerative receiver are demonstrated, where each is specifically designed to operate in the near-threshold region. The low-VDD transmitter utilizes a sub-harmonic injection-locked ring oscillator, edge combiner for frequency multiplication, and class-C power amplifier. The low-VDD receiver introduces a replica super-regenerative receiver as a method to reject common-mode noise sources, such as supply/substrate coupling, thereby reducing undesired self-oscillations and improving BER. Designed in a 90-nm CMOS process, the test-chip measurements show a sensitivity of -80 dBm at 500 kb/s and -65 dBm at 1 Mb/s, respectively, at a BER less than 10-3, with 340 μW total power.

Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS

A CMOS impulse radio transceiver that uses chaotic pulse-position modulation for ultra-wideband (UWB) communications is designed. While the conventional direct-sequence spread-spectrum (DSSS) system dither the time delay between impulses by a pseudorandom number generator, chaotic modulation dithering uses a predictable but wideband nonlinear function, resulting in significant improvements in spectral spreading. The nonlinear functions implemented in the transmitter and receiver use a tent map, requiring only a voltage-to-time and time-to-voltage converter. A R-S latch enables the parallel implementation of two consecutive states of the tent map. Due to the predictable nature of the nonlinear mapping functions, receiver synchronization time is achieved in Order (0) time, as opposed to the conventional DSSS correlating receivers. Implemented in a 0.25 μm CMOS technology, the transceiver achieves an average data rate of 25 Mbps and a BER <; 10e-9, while sending 0.4-ns wide UWB baseband impulses.

A 90nm-CMOS, 500Mbps, fully-integrated IR-UWB transceiver using pulse injection-locking for receiver phase synchronization

A fully-integrated, 3.1–5GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR). Occupying 2mm2 die area, the transceiver achieves a maximum data rate of 500 Mbps, energy efficiency of 0.18nJ/b at 500Mbps, and a RX-BER of 10−3 across a distance of 10cm at 125Mbps.

Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband(IR-UWB) transceivers

This paper presents a novel CMOS 2-tap equalizer for combating multipath interference in impulse radio, ultra-wideband (IR-UWB) transceiver systems. The equalizer is composed of pulse width control, pulse tap delay control, pulse sign inversion, and current mode logic (CML) summation for data transmission. SpectreRF post-layout simulation in a 90-nm CMOS technology shows that the transceiver operates up to a 2Gbps data rate by removing the 1st and 2nd multipath reflections, illustrating significant signal-to-noise (SNR) improvement when compared with a conventional transmitter.

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS

A reconfigurable, 3-50GHz all-digital impulse generator for short-distance wireless communications is designed in 40nm-CMOS. Digital back-gate biasing is used for raised-cosine envelope pulse-shaping to achieve better spectral-mask efficiency. Pulse duration, duty-cycle, and operating frequency are digitally programmable, in order to satisfy multi-band standards compatibility. An asymmetric inverter design within the Mono-Pulse-Generator (MPG) eliminates undesired glitches for the complementary clock edge. Occupying 350µm×260µm die area, the proposed impulse transmitter achieves a maximum data-rate of 3Gbps and an energy-efficiency of 0.5pJ/pulse for a 25GHz carrier frequency.

Measurement and characterization of ultra-wideband wireless interconnects within active computing systems

This paper presents experimental measurements of ultra-wideband (UWB) wireless interconnects within an operational computer system chassis. Using an impulse-radio ultra-wideband (IR-UWB) 3–5GHz transceiver, this paper analyzes and verifies the implementation of high-bandwidth wireless communications within an enclosed, heavy multipath, metallic environment such as a computer server chassis. Bit-error-rate (BER) and recovered clock jitter were measured at various positions within the computer chassis. The results show a 6X improvement in BER after applying the equalizer to the noisy channel while the motherboard is fully operating.

Design challenges for ultra-wideband wireless communications within a computer chassis

Conventional metal wiring is becoming an inevitable difficulty for a computing platform. This paper presents an Ultrawideband (UWB) wireless interconnection solution. The channel characteristics within a computer chassis is analyzed, including the path loss, multipath reflections and electromagnetic interferences (EMI). To address the above problems, an IR-UWB transceiver is proposed with equalization in transmitter to relax the multipath reflections and pulse injection-locking for receiver clock recovery and synchronization. The transceiver achieved a significant power saving for high data rate (up to 500Mbps) demodulation.

Ultra Wideband RF Transceiver Design in CMOS Technology

UWB (Ultra-Wideband) is one of the WPAN (Wireless Personal Area Network) Technologies; its main applications include imaging systems, vehicular radar systems and communications and measurement systems. Ever since the FCC released unlicensed spectrum of 3.1-10.6 GHz for UWB application in 2002, UWB has received significant interest from both industry and academia. Comparing with traditional narrowband WPANs, (e.g. Bluetooth, Zigbee, etc.), the most significant characteristics of UWB are ultra-wide bandwidth (7.5 GHz) and low emitted spectrum density (-41.3 dBm/MHz). According to Shannon-Hartley theorem (Wikipedia, 2010), through an AWGN (Additive White Gaussian Noise) channel, the maximum rate of clean (or arbitrarily low bit error rate) data is limited to