Jay P. Sage

Low T/sub c/ superconductive circuits fabricated on 150-mm-diameter wafers using a doubly planarized Nb/AlO/sub x//Nb process

We have used a doubly planarized all-refractory technology for superconductive electronics (DPARTS) process to fabricate mixed-signal circuits that have more than 200 junctions per circuit and operate at 2 GHz. A 150-mm-diameter wafer can produce more than 400 chips, each 5 mm on an edge. The junctions had a critical current density of 1.7 kA/cm/sup 2/. The wafers were evaluated at room temperature, both in- and post-process. In-process testing was used to detect parameter shifts during processing, while post-process testing used an automated testing station to test more than 3500 structures across each completed wafer and thus establish a large set of statistical data for studying the spread and targeting of parameter values. The circuits were fabricated in a class-10 clean room in which 0.25 /spl mu/m CMOS and CCD devices were also produced. The DPARTS process could also be used for sub-/spl mu/m fabrication, as it includes optical lithography with an i-line stepper; chemical-mechanical planarization at two levels; a self-aligned via process; and dry, anisotropic etching for all metal etching and via definition steps. The use of 150-mm-diameter wafers ensures that this process will be able to exploit technological advances in the standard silicon tool set as improvements become available. The results demonstrated here are a necessary precondition to yielding large volumes of superconductive electronic circuits containing devices with sub-/spl mu/m dimensions.

Resonant-tunneling-diode relaxation oscillator☆

Abstract Monolithic resonant-tunneling-diode (RTD) relaxation oscillators are fabricated. The highest repetition rate of this pulse generator is 6.7 GHz with a pulse width of approximately 60 ps. Oscillators with an RTD connected to an off-chip transmission line have been operated at a rate as low as 34 MHz while maintaining a similar pulse width. Characterization aided with simulations provides a better understanding of the RTD relaxation oscillator and the effects of the RTD characteristics on the performance of the oscillator.

Dewar-to-dewar data transfer at GHz rates

Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.

Evaluation of critical current density of Nb/Al/AlO/sub x//Nb Josephson junctions using test structures at 300 K

We have designed and fabricated test structures that allow the determination of the critical current density and processing run-out of low T/sub c/ Josephson junctions based only on room-temperature measurements. We demonstrated that the 300 K tunneling conductance of a junction barrier is proportional to the critical current at 4.2 K. This testing technique greatly reduced the time required to characterize a process wafer. In one demonstration we tested hundreds of devices across a 150-mm-diameter wafer in less than an hour. In another we used a selective niobium anodization process with only two mask levels to determine the critical current density of a Nb/AlO/sub x//Nb trilayer within a day of its deposition. We have also used automated probing stations to decrease testing delays further and thus to improve process cycle time.

Design, fabrication, and testing of a high-speed analog sampler

The authors describe the design, fabrication, and first successful operation in the gigahertz frequency range of a Josephson-junction-based sampling circuit designed to provide 6 b of resolution ( approximately 35 dB) and 10 GHz or more of bandwidth. The first experimental demonstration of a prototype circuit sampling a sine wave at up to 1 GHz is reported. This sampler has properties that make it amenable to incorporation into complex, mixed-analog/digital integrated circuits. Such a circuit can be used in the implementation of such signal processing subsystem components as a transient waveform data recorder, a programmable analog-binary correlator, and a flash analog-to-digital converter.<<ETX>>

Microwave intermodulation products and excess critical current in YBa2Cu3O7−x Josephson junctions

Third‐order intermodulation power generated by a Josephson junction in an YBa2Cu3O7−x microwave resonator is measured and compared to a calculation based on the resistively shunted junction model. The results agree with junction parameters determined by power‐dependent loss measurements on the same resonator at temperatures near the transition temperature TC, but measurements below TC/2 suggest that excess critical current, which does not contribute to the nonlinear properties of the junction, occurs at lower temperatures. Local heating is suggested to explain this feature. These results are relevant to the coupled‐grain model used to describe microwave properties of high‐TC superconductors and to the understanding of Josephson junctions in these materials.

Mixed analog-digital niobium superconductive circuits for a 2-gigachip-per-second spread-spectrum modem

This paper describes the architecture and operation of a superconductive programmable matched filter that provides rapid synchronization information and data demodulation for a 2-GHz spread-spectrum modem. Results are reported for the first circuit fabrication runs using a new doubly planarized process. With the exception of circuits containing layout errors, all circuits have performed as intended and with characteristics that match well the predictions of JSIM simulations. The MVTL digital components and the buffer between the digital and analog circuits have been demonstrated for the first time. The seven-stage MVTL shift register in a complete prototype filter was operated at 1 GHz. In addition, combinations of (1) the MVTL digital shift register and the buffer and (2) the buffer and the T/H cell have been operated successfully, demonstrating that all of the components in the filter core will work together.

Molecular-beam epitaxial regrowth on oxygen-implanted GaAs substrates for device integration

Device-quality layers were regrown on GaAs wafers by molecular-beam epitaxy over conductive pregrown areas and on selectively patterned high-resistivity areas formed by oxygen implantation. The regrowth over both areas resulted in comparable device-quality GaAs. The high resistivity of the oxygen-implanted area was maintained after the regrowth and no oxygen incorporation was observed in the regrown layer. The cutoff frequency of a 1.5-μm-gate metal-semiconductor field-effect transistor fabricated on the regrown layer over the high-resistivity areas is 7 GHz. This demonstration shows that planar technology can be used in epitaxial regrowth, simplifying the integration of vastly different devices into monolithic circuits.

Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing non-compliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.

Demonstration of charge-coupled devices in fully depleted SOI

This paper discusses on demonstration of charge-coupled devices in fully depleted SOI. CCDs implemented in FDSOI are expected to operate up to higher speeds than conventional bulk surface-channel CCDs. While FDSOI CCDs retain the high linearity and charge storage density of surface-channel CCDs, the buried oxide (BOX) layer allows strong fringing electric fields to penetrate beneath the gates and accelerate the transfer of charge from gate to gate. The simulation results illustrate the speed improvement with increasing BOX thickness. The improvement saturates when the BOX thickness becomes comparable to the gate length.