Terence J. Weir

Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc <; 2 K) MoNx layer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density Jc of 100 μA/μm2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, Ic and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.

Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al–

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm2 to 50 kA/cm2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 106 JJ/cm2 and 193-nm photolithography for JJ definition are discussed.

\hbox{AlO}_{\rm x}\hbox{/Nb}

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106 Josephson junctions per cm2 are discussed.

Josephson Junctions for VLSI Circuits

A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm−2 and approaches the depairing current density of Nb films.

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process With 8 Niobium Layers

We have investigated the driven dynamics of a superconducting flux qubit that is tunably coupled to a microwave resonator. We find that the qubit experiences an oscillating field mediated by off-resonant driving of the resonator, leading to strong modifications of the qubit Rabi frequency. This opens an additional noise channel, and we find that low-frequency noise in the coupling parameter causes a reduction of the coherence time during driven evolution. The noise can be mitigated with the rotary-echo pulse sequence, which, for driven systems, is analogous to the Hahn-echo sequence.

Deep sub-micron stud-via technology of superconductor VLSI circuits

Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.

Driven Dynamics and Rotary Echo of a Qubit Tunably Coupled to a Harmonic Oscillator

This paper discusses on demonstration of charge-coupled devices in fully depleted SOI. CCDs implemented in FDSOI are expected to operate up to higher speeds than conventional bulk surface-channel CCDs. While FDSOI CCDs retain the high linearity and charge storage density of surface-channel CCDs, the buried oxide (BOX) layer allows strong fringing electric fields to penetrate beneath the gates and accelerate the transfer of charge from gate to gate. The simulation results illustrate the speed improvement with increasing BOX thickness. The improvement saturates when the BOX thickness becomes comparable to the gate length.