Jayita Das

Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures

In this paper, we report magnetic quantum cellular automata (MQCA) realization using multi-layer cells with tilted polarizer reference layer with a particular focus on the critical need to shift toward the multi-layer cells as elemental entities from the conventional single-domain nanomagnets. We have reported a novel spin-transfer torque current-induced clocking scheme, theoretically derived the clocking current, and shown the reduction in power consumption achieved against the traditional mechanism of clocking using magnetic fields typically generated from overhead or underneath wires. We have modeled the multi-layer cell behavior in Verilog-A along with the underlying algorithm used in implementing the neighbor interaction between the cells. This paper reports the switching and clocking current magnitudes, their direction and the power consumption associated with switching and clocking operation. Finally, we present the simulation results from Verilog-A model of switching, clocking and neighbor interaction. Low power consumption due to spin transfer torque current induced switching and clocking along with the reasonable magneto-resistance (MR) distinguishing the two energy minimum states of the device, make these devices a promising candidate in MQCA realization.

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture

Dipolar magnetic coupling between single layer nanomagnets is used in nanomagnetic logic (NML). Apart from writing and reading, nanomagnets are also clocked using external magnetic fields generated by current carrying wires. The related current ranges in mA and consumes large power. Also, the fields cannot sharply terminate at boundaries between nanomagnets that are required to be in different clock zones. The above concerns motivated us to look into alternate magnetic devices to realize magnetic logic. We therefore suggested miltilayer magnetic tunnel junctions (MTJs) for logic. We have observed that MTJ free layers can interact with their neighbors through magnetic coupling. In this paper we have proposed use of this coupling for effective logic computation. MTJs are also CMOS friendly, a property that we used to write, clock and read from logic. CMOS integration also improves control over individual elements in logic. In this paper we have used these properties to present a novel CMOS-MTJ integrated architecture that: a) computes logic using magnetic coupling between MTJs and b) writes, clocks and reads from logic using spin transfer torque (STT) current that is more energy efficient. A feasibility study of this CMOS-MTJ integration in 22 nm CMOS technology node is also presented. The proposed architecture achieves an energy reduction >;95% in adders and multipliers when compared to traditional designs using single layer nanomagnets.

MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS

This manuscript addresses a novel MRAM-based physically unclonable function (PUF). The PUF responses are generated using the unique energy-tilt, which is an outcome of the random geometric variations in the MRAM cells. We have verified relevant attributes of this PUF through extensive magnetic simulations and in-house fabrication results. Our fabricated PUF cells generate entropy as high as 0.99, which is comparable to most of its competitors. To our knowledge, the footprint of the PUF cells is also lower than the majority of silicon PUFs. Also, the authentication control algorithm for this PUF requires very low additional control-steps. We conclude our discussion of this novel PUF with a study of authentication overhead and protocols required by the PUF system in terms of area, power, and delay.

A novel geometry based MRAM PUF

In this paper we have proposed a novel MRAM based physically unclonable function (PUF) using the uncontrollable geometric variation in MRAM cells. The geometric variations generate a preferred ground state in every MRAM cell that we have used for the novel PUF. We have also analyzed the security properties of this PUF using a combination of simulation and fabrication methods. Results show an intra-distance of 0.0225 and an inter-distance of 0.47 for this PUF.

Nano Magnetic STT-Logic Partitioning for Optimum Performance

Magnetoresistive RAMs (MRAMs) are the new generation of nonvolatile memories that use magnetic tunnel junctions (MTJs) to store bit information. Horizontal (bit and source) and vertical (word) lines partition the MRAM into a 2-D grid similar to a conventional memory. This paper relies on a logic-in-memory architecture where MRAM cells are placed in close proximity so that they can behave both as logic elements and as memory bits. When the clock signal is active the cells compute logic, while at other times the cells store the data in them and behave as memory. Using these MRAM cells, in this paper, we have designed two fundamental components in datapath and logic circuits, the XOR and majority. By transferring logic responsibilities between the metal lines, CMOS peripherals and the MTJs, we have achieved a significant reduction in MTJ cell count, energy, and delay over previous designs. For example, an energy savings of more than 75% and a cell reduction of more than 81.25% are obtained for a 2-input XOR in standalone mode of operation. Though this hybrid sharing of responsibilities between the MTJs and CMOS has apparently increased the overhead on CMOS, it has however reduced the net power consumption in the CMOS peripherals. This happens because the CMOS now has a fewer number of cells to control. The reduction in the CMOS power varies from close to 50% for a 2-input XOR to greater than 10% for a majority. In addition, the designs also obey the rules of hierarchical modeling which helped us to use the novel 2-input XORs as bricks for designing the novel 3-input XOR. Again a 3-input XOR and majority are used to custom develop a one-bit full adder. Together with an inter-cell spacing of 20 nm and low power spin transfer torque current-driven write and clock operations, the novel designs presented in this paper has the potential to target the low energy and high density logic-in-memory applications.

Design of NML Circuits based on M-RAM

NanoMagnet Logic (NML) is an emerging technology that allows to design digital circuits using nanomagnets. Each magnet has only two possible states and encodes digital information without the need for currents or voltages. This behavior differentiates NML circuits from charge based technologies. The advantages provided by NML circuits are a possible very low power consumption, and the ability to mix logic and memory in the same device. While a rich experimental activity on NML circuits can be found in literature, the feasibility of a complete NML system remains to be demonstrated yet. In this work we explore the possibility of implementing NML logic circuits based on the physical structure of Magnetic RAM (M-RAM). The advantages are twofold: First, M-RAM is a well developed technology, ready for the commercial stage, second it intrinsically provides an interface toward the CMOS world. To demonstrate the feasibility of NML circuits based on M-RAM we have designed a 3-input Ex-OR gate, using two different physical layouts for control signals. The first solution is strictly based on the M-RAM structure; the second solution requires a more complex fabrication process but leads to a smaller area. Circuits are simulated using VHDL language, with the aid of a tool that we have developed which automatically generates the VHDL code starting from the circuit layout. Overall, the solution here presented is a considerable step-forward toward the development of a complete magnetic circuit.

A novel design concept for high density hybrid CMOS-nanomagnetic circuits

In this paper we have presented a novel design concept in hybrid CMOS-Nanomagnetic logic architecture and have shown it for a 2-input XOR. This paradigm is based on Shannons expansion theorem and distributes the role of logic computation between the spin transfer torque magnetic tunnel junctions (STT-MTJs) and the CMOS metal lines. A 81.25% reduction in cell count and more than 75% reduction in energy consumption is achieved with this design strategy. The concept can be extended to any n-input XOR and other suitable logic functions.

Low power CMOS-magnetic nano-logic with increased bit controllability

Conventional magnetic logic using single-domain nanomagnets face severe challenges from power consumption, during field induced writing and clocking, and from poor selectivity over the logic cells. In this paper we report a novel CMOS integrated nanomagnetic logic architecture using Magnetic Tunnel Junctions (MTJs) as elemental cells. The integration details with 22nm CMOS technology is discussed and the feasibility of integration studied. The access transistors of the MTJs provide certain improvement in controllability over the bits of the logic. Increased controllability prevents unnecessary switching of the cells, as discussed in the paper, and hence saves power.

RECENT TRENDS IN SPINTRONICS-BASED NANOMAGNETIC LOGIC

With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.

Addressing the layout constraint problem when cascading logic gates in nanomagnetic logic

Nanomagnetic Logic (NML) uses ferromagnetic and anti-ferromagnetic coupling to propagate information and to compute logic. In this paper we have addressed a layout constraint problem that surfaces in NML due to magnetic coupling based logic computation. The layout constraint problem poses a severe challenge to designing high density low power cascaded logic. After defining the problem and explaining its cause and impact on NML designs, we have proposed a novel solution to the problem. This helps to design high density and low power cascaded NML circuits.