Sanjukta Bhanja

Estimation of Upper Bound of Power Dissipation in QCA Circuits

Quantum-dot cellular automata (QCA) is a field-coupled computing paradigm. States of a cell change due to mutual interactions of either electrostatic or magnetic fields. Due to their small sizes, power is an important design parameter. In this paper, we derive an upper bound for power loss that will occur with input change, even with the circuit staying at respective ground states before and after the change. This bound is computationally efficient to compute for large QCA circuits since it just requires the knowledge of the before and after ground states due to input change. We categorize power loss in clocked QCA circuits into two types that are commonly used in circuit theory: switching power and leakage power. Leakage power loss is independent of input states and occurs when the clock energy is raised or lowered to depolarize or polarize a cell. Switching power is dependent on input combinations and occurs at the instant when the cell actually changes state. Total power loss is controlled by changing the rate of change of transitions in the clocking function. Our model provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in nonadiabatic operations and gives us the upper bound of power expended. We derive expressions for upper bounds of switching and leakage power that are easy to compute. Upper bounds obviously are pessimistic estimates, but are necessary to design robust circuits, leaving room for operational manufacturing variability. Given that thermal issues are critical to QCA designs, we show how our model can be valuable for QCA design automation in multiple ways. It can be used to quickly locate potential thermal hot spots in a QCA circuit. The model can also be used to correlate power loss with different input vector switching; power loss is dependent on the input vector. We can study the tradeoff between switching and leakage power in QCA circuits. And, we can use the model to vet different designs of the same logic, which we demonstrate for the full adder.

QCAPro - An error-power estimation tool for QCA circuit design

In this work we present a novel probabilistic modeling tool (QCAPro) to estimate polarization error and non-adiabatic switching power loss in Quantum-dot Cellular Automata (QCA) circuits. The tool uses a fast approximation based technique to estimate highly erroneous cells in QCA circuit design. QCAPro also provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in non-adiabatic operations and provides an upper bound of power expended. QCAPro can be used to estimate average power loss, maximum and minimum power loss in a QCA circuit during an input switching operation. This work will provide a good platform for researchers who wish to study polarization error and power dissipation related issues in QCA circuits.

Scalable probabilistic computing models using Bayesian networks

As technology scales below 100nm and operating frequencies increase, correct operation of nano-CMOS will be compromised due reduced device-to-device distance, imperfections, and low noise and voltage margins. Unlike traditional faults and defects, these errors are expected to be transient in nature. Unlike radiation related upset errors, the propensity of these transient errors will be higher. Due to these highly likely errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic events. We propose the formalism of probabilistic Bayesian networks (BNs), which also forms a complete joint probability model, for probabilistic computing. Using the exact probabilistic inference scheme known as clustering, we show that for a circuit with about 250 gates the output error estimation time is less than three seconds on a 2GHz processor. This is three orders of magnitude faster than a recently proposed method for probabilistic computing using transfer matrices

Switching activity estimation of VLSI circuits using Bayesian networks

Switching activity estimation is an important aspect of power estimation at circuit level. Switching activity in a node is temporally correlated with its previous value and is spatially correlated with other nodes in the circuit. It is important to capture the effects of such correlations while estimating the switching activity of a circuit. In this paper, we propose a new switching probability model for combinational circuits that uses a logic-induced directed-acyclic graph (LIDAG) and prove that such a graph corresponds to a Bayesian network (BN), which is guaranteed to map all the dependencies inherent in the circuit. BNs can be used to effectively model complex conditional dependencies over a set of random variables. The BN inference schemes serve as a computational mechanism that transforms the LIDAG into a junction tree of cliques to allow for probability propagation by local message passing. The proposed approach is accurate and fast. Switching activity estimation of ISCAS and MCNC circuits with random and biased input streams yield high accuracy (average mean error=0.002) and low computational time (average elapsed time including CPU, memory access and I/O time for the benchmark circuits=3.93 s).

Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures

In this paper, we report magnetic quantum cellular automata (MQCA) realization using multi-layer cells with tilted polarizer reference layer with a particular focus on the critical need to shift toward the multi-layer cells as elemental entities from the conventional single-domain nanomagnets. We have reported a novel spin-transfer torque current-induced clocking scheme, theoretically derived the clocking current, and shown the reduction in power consumption achieved against the traditional mechanism of clocking using magnetic fields typically generated from overhead or underneath wires. We have modeled the multi-layer cell behavior in Verilog-A along with the underlying algorithm used in implementing the neighbor interaction between the cells. This paper reports the switching and clocking current magnitudes, their direction and the power consumption associated with switching and clocking operation. Finally, we present the simulation results from Verilog-A model of switching, clocking and neighbor interaction. Low power consumption due to spin transfer torque current induced switching and clocking along with the reasonable magneto-resistance (MR) distinguishing the two energy minimum states of the device, make these devices a promising candidate in MQCA realization.

QCA Circuits for Robust Coplanar Crossing

In this paper, different circuits of Quantum-dot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. Coplanar crossing is one of the most interesting features of QCA because it allows for mono-layered interconnected circuits, whereas CMOS technology needs different levels of metalization. However, the characteristics of the coplanar crossing make it prone to malfunction due to thermal noise or defects. The proposed circuits exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. A Bayesian Network (BN) based simulator is utilized for evaluation; results are provided to assess robustness in the presence of cell defects and thermal effects. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. Simulation of the wire crossing circuits at different operating temperatures is provided with respect to defects and a quantitative metric for performance under temperature variations is proposed and assessed.

Magnetic cellular automata coplanar cross wire systems

Quantum cellular automata has proposed an exclusive architecture where two coplanar perpendicular wires have the ability to intersect one another without signal degradation. The physical realization of cross wire architectures has yet to be implemented and researchers share concerns over the reliability of such a system. Here we have designed a coplanar cross wire layout for magnetic cellular automata (MCA) and have fabricated two different systems. The first system was implemented via two ferromagnetic coupled coplanar crossing wires and demonstrated all possible logic combinations. The second more complex cross wire system consisted of nine junctions and one hundred and twenty single domain nanomagnets. The complex system’s ability to reach an energy minimum combined with the demonstration of all combinations of the smaller system leads us to conclude that a cross wire system is physically feasible and reliable in MCA.

Probabilistic Modeling of QCA Circuits Using Bayesian Networks

To push the frontiers of quantum-dot cellar automata (QCA) based circuit design, it is necessary to have design and analysis tools at multiple levels of abstractions. To characterize the performance of QCA circuits it is not sufficient to specify just the binary discrete states (0 or 1) of the individual cells, but also the probabilities of observing these states. We present an efficient method based on graphical probabilistic models, called Bayesian networks (BNs), to model these steady-state cell state probabilities, given input states. The nodes of the BN are random variables, representing individual cells, and the links between them capture the dependencies among them. BNs are minimal, factored, representation of the overall joint probability of the cell states. The method is fast and its complexity is shown to be linear in terms of the number of cells. This BN model allows us to analyze clocked QCA circuits in terms of quantum- mechanical quantities, such as steady-state polarization and thermal ratios for each cell, without the need for full quantum-mechanical simulation, which is known to be very slow and is best postponed to the final stages of the design process. We can also estimate the most likely (or ground) state configuration for all the cells and the lowest energy configuration that results in output errors. We validate the model with steady-state probabilities computed by the Hartree-Fock self-consistent approximation (HT-SCA). Using full adder designs, we demonstrate the ability to compare and contrast QCA circuit designs with respect to the variation of the output state probabilities with temperature and input. We also show how weak spots in clocked QCA circuit designs can be found using our model by comparing the (most likely) ground-state configuration with the next most likely energy state configuration that results in output error

Dependency preserving probabilistic modeling of switching activity using bayesian networks

We propose a new switching probability model for combinational circuits using a logic-induced-directed-acyclic-graph (LIDBG) and prove that such a graph corresponds to a Bayesian network guaranteed to map all the dependencies inherent in the circuit. This switching activity can be estimated by capturing complex dependencies (spatiotemporal and conditional) among signals efficiently by local message-passing based on the Bayesian networks. Switching activity estimation of ISCAS and MCNC circuits with random input streams yield high accuracy (average mean error=0.002) and low computational time (average time=3.93 seconds).

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture

Dipolar magnetic coupling between single layer nanomagnets is used in nanomagnetic logic (NML). Apart from writing and reading, nanomagnets are also clocked using external magnetic fields generated by current carrying wires. The related current ranges in mA and consumes large power. Also, the fields cannot sharply terminate at boundaries between nanomagnets that are required to be in different clock zones. The above concerns motivated us to look into alternate magnetic devices to realize magnetic logic. We therefore suggested miltilayer magnetic tunnel junctions (MTJs) for logic. We have observed that MTJ free layers can interact with their neighbors through magnetic coupling. In this paper we have proposed use of this coupling for effective logic computation. MTJs are also CMOS friendly, a property that we used to write, clock and read from logic. CMOS integration also improves control over individual elements in logic. In this paper we have used these properties to present a novel CMOS-MTJ integrated architecture that: a) computes logic using magnetic coupling between MTJs and b) writes, clocks and reads from logic using spin transfer torque (STT) current that is more energy efficient. A feasibility study of this CMOS-MTJ integration in 22 nm CMOS technology node is also presented. The proposed architecture achieves an energy reduction >;95% in adders and multipliers when compared to traditional designs using single layer nanomagnets.