Jaynarayan T. Tudu

On Minimization of Peak Power for Scan Circuit during Test

Scan circuit generally causes excessive switching activitycompared to normal circuit operation. The higher switchingactivity in turn causes higher peak power supply currentwhich results into supply voltage droop and eventuallyyield loss. This paper proposes an efficient methodologyfor test vector re-ordering to achieve minimum peak powersupported by the given test vector set. The proposed methodologyalso minimizes average power under the minimumpeak power constraint. A methodology to further reduce thepeak power, below the minimum supported peak power, byinclusion of minimum additional vectors is also discussed.The paper defines the lower bound on peak power for agiven test set. The results on several benchmarks shows thatit can reduce peak power by up to 27%.

Graph theoretic approach for scan cell reordering to minimize peak shift power

Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power

Traditionally, serial scan architecture have been predominantly used as a DFT technique for most of the designs. However, shrinking technology and increasing design complexity has brought a set of new test challenges. It initiates new research direction to explore innovative DFT architecture. This paper proposes a new DFT architecture, named as Joint-scan. The proposed architecture provides a solution for the test time, test data volume, and test power problems simultaneously. The primary idea here is to bring in the key advantages of serial scan and random access scan in a single architecture. The effectiveness of the proposed architecture has been demonstrated through experimental results by comparing with the state-of-the-art random access scan, and multiple sequential scan architecture. The results show promising reduction in test time, data volume, and test power.

On determination of instantaneous peak and cycle peak switching using ILP

Power has becomes one of the crucial parameter while designing a SOC ICs. Power analysis of a circuit is important for reliability check, better design of power distribution network, packaging decisions and to solve power issues during test. High switching at a time demands high instantaneous current from power supply network. Which gates experience Vdd drop leading to increase in delay of the circuit. Power consumed by circuit is proportional to switching activity at gate outputs and capacitance associated with it. Most of the previous work consider switching activity over entire clock period, however this is very pessimistic approach. All gates do not switch at the same time because of associated delays, thus peak switching occurring at an instant of time should be considered. In this paper we formulate an Integer Linear Programming for computing maximum transitions in the circuit at any instant time as well as during entire clock period. This method identifies a vector pair which provides the highest activity in the circuit. The proposed method captures the impact of glitches occurring during signal propagation. Our analysis shows that the maximum 75% of total gates can switch at any time instant and the maximum 625% of total gates can switch during clock period.

ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits

Dynamic power estimation is a critical requirement in the design of digital logic for effective design decision. The brute-force way of estimating the power is to apply all the possible input vectors. Since the complexity of modern integrated circuits follow Moores trend this technique can no longer be applied for computationally efficient and accurate power estimation. In the literature different techniques are reported for estimating the power either by generating the worst power consuming input vector or by applying some probability based technique. We have attempted to generate input vectors that result in maximum possible toggling for combinational circuits. In this work, we have modeled combinational circuits using binary integer linear program(BILP) and solved it using the mixed integer linear programming solver CPLEX. Experimental results on ISCAS-85 benchmarks show that the input vectors generated by our methodology result into maximally possible toggling in the circuit for most of the benchmark circuits.

A Cost Effective Technique for Diagnosis of Scan Chain Faults

Scan based diagnosis plays a critical role in failure mode analysis for yield improvement. However, as the logic circuitry associated with scan chains constitute a significant fraction of a chip’s total area the scan chain itself can be subject to defects. In some cases, it has been observed that scan chain failures may account up to \(50\%\) of total chip failures. Hence, scan chain testing and diagnosis have become very crucial in recent years. This paper proposes a hardware-assisted low complexity and area efficient scan chain diagnosis technique. The proposed technique is simple to implement and provides maximum diagnostic resolution for stuck-at faults. The proposed technique can be further extended to diagnose scan chain’s timing faults.

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.

Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP

Due to shrinking size of transistor and increasing circuit complexity the instantaneous power became a concern for circuit reliability. Higher IR-drop/Ground bounce induces unpredictable delay and can cause soft error. Higher V dd can cause thermal hot-spot. Appropriate selection of V dd and design of power distribution network(PDN) plays crucial role in alleviating such issues. The design of an efficient PDN entirely depend on the knowledge of power budget and dynamic behaviour of instantaneous activity.

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

On selection of state variables for delay test of identical functional units

Multiple copies of the same functional units are common in todays design. It allows us to reduce golden reference storage by performing comparison of output response of the identical circuits when identical input sequence is applied to them. We present output response comparison scheme for identical sequential circuits for delay test using static transition probability. This allows us to make selection independent of the input sequence.