Satyadev Ahlawat

A low cost technique for scan chain diagnosis

Scan based diagnosis plays a critical role in yield enhancement of sub-nanometer technology based chips. However, the scan chain itself can be subject to defects due to the large logic circuitry associated with it which constitute a significant fraction of total chip area. In some cases, it has been observed that scan chain failures may account for 30% to 50% of chip failures. Hence, scan chain testing and diagnosis has become very crucial in recent years. In this paper, we propose a hardware-assisted low cost and low complexity scan chain diagnosis technique. The proposed technique is very simple in operation and provides maximum resolution for stuck-at fault diagnosis.

A Cost Effective Technique for Diagnosis of Scan Chain Faults

Scan based diagnosis plays a critical role in failure mode analysis for yield improvement. However, as the logic circuitry associated with scan chains constitute a significant fraction of a chip’s total area the scan chain itself can be subject to defects. In some cases, it has been observed that scan chain failures may account up to \(50\%\) of total chip failures. Hence, scan chain testing and diagnosis have become very crucial in recent years. This paper proposes a hardware-assisted low complexity and area efficient scan chain diagnosis technique. The proposed technique is simple to implement and provides maximum diagnostic resolution for stuck-at faults. The proposed technique can be further extended to diagnose scan chain’s timing faults.

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.

An efficient test technique to prevent scan-based side-channel attacks

Almost every complex circuit today employs scan-based Design-for-Testability (DFT) architecture to enhance controllability and observability for every flip-flop in the design, thereby improve the testability. However, the DFT structure can also be exploited to mount side-channel attacks to retrieve the secret key stored in a cryptographic chip, thus compromising its security. In this paper, we propose a new secure scan test architecture which isolates the encryption key whenever the cryptographic chip is switched to test mode. The encryption key remains isolated during the whole scan test process. It also clears the last functional states of the security sensitive scan cells as soon as the scan test mode is activated. The proposed secure scan test approach is capable of exercising all kinds of conventional stuck-at and timing test. The proposed approach has minimal hardware overhead and it is capable of preventing existing scan-based side channel attacks.

Guided shifting of test pattern to minimize test time in serial scan

Scan test time has always been one of the priority issues for test researchers because it directly impact cost of the design. In this work we have addressed the issue through scan chain and test pattern reordering. The idea of limited scan shift is explored. We have proposed a graph theoretical framework for reordering of scan chain and test pattern. Graph theoretic problem is formulated for each, scan chain and test pattern, reordering. For each of the formulated problems corresponding approximation algorithms are proposed. The experimental results show that the proposed methodology reduces the scan shift time compared to the ordering provided by atpg tool.

On minimization of test power through modified scan flip-flop

Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified scan flip-flop design which uses a low cost dynamic slave latch to shift the test vectors and allows the static slave latch to retain the responses from the previous test vector. Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power. Furthermore the proposed scan flip flop design does not use any gating element in functional path, and hence the functional performance overhead is comparatively very less than the previously proposed output gating techniques so far.

Enabling LOS delay test with slow scan enable

Delay defects can be detected using Launch-off-capture (LOC) and Launch-off-shift (LOS) based delay test techniques. In terms of delay test coverage and test set size, LOS is more effective compared to LOC. However, to exercise LOS test a high speed scan enable signal is required. The cost of implementing a high speed global scan enable signal is prohibitively high. In practice, most of the commercial designs employing full scan design support only LOC based delay test. In this paper, we propose a new scan flip-flop design that is capable of exercising both LOS and LOC based delay test with a slow scan enable signal. The proposed design can achieve much higher delay fault coverage by exercising both LOS and LOC test. Furthermore, in a mixed mode scan test environment the proposed scan flip-flop can be used both as a serial scan cell as well as a random access scan (RAS) cell.