Je-Hoon Lee

Stabilization of LCD devices via geometric alteration

Glass bending in LCD displays is an inherent problem that has challenged many engineers. As a solution to this problem, we propose a methodology that can tackle the root of the phenomenon in terms of linear elastic beam theory. Using this hypothesis, we devised a background theory and a solution. In this paper, we present a glass panel to which geometrical changes, such as furrow, groove, and curb have been applied. These geometrical changes are applied to the nonactive area of the glass panel. To confirm the validity of our approach, we conducted simulation tests as well as hands-on experiments to observe the thermo-mechanical behavior of the device under various conditions. The simulation results using the Ansys simulator show that the proposed technique can reduce the deformation level of panel bending by 40%. In the experiment using a bare cell with polarizer films attached and with performing the high temperature reliability test, the deformation level of panel bending is reduced by half compared to the reference glass panel without any geometric alteration.

Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design

This paper proposes a hardware-software (HW-SW) co-simulation framework that provides a unified system-level power estimation platform for analyzing efficiently both the total power consumption of the target SoC and the power profiles of its individual components. The proposed approach employs the trace-based technique that reflects the real-time behavior of the target SoC by applying various operation scenarios to the high-level model of target SoC. The trace data together with corresponding look-up table (LUT) is utilized for the power analysis. The trace data is also used to reduce the number of input vectors required to analyze the power consumption of large H/W designs through the trade-offs between the signal probability in the trace results and its effect on the power consumption. The effect of cache miss on power, occurring in the S/W program execution, is also considered in the proposed framework. The performance of the proposed approach was evaluated through the case study using the SoC design example of IEEE 802.11a wireless LAN modem. The case study illustrated that, by providing fast and accurate power analysis results, the proposed approach can enable SoC designers to manage the power consumption effectively through the reconstruction of the target SoC. The proposed framework maps all hardware IPs into FPGA. The trace based approach gets input vectors at transactor of the each IP and gets power consumption indexing a LUT. This hardware oriented technique reports the power estimation result faster than the conventional ones doing it at S/W level.

Design of High-performance Parallel BCH Decoder for Error Collection in MLC Flash Memory

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

A Segmented Leap-Ahead LFSR Pseudo-Random Number Generator

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.

Wake-up Algorithm of Wireless Sensor Node Using Geometric Probability

Efficient energy management becomes a critical design issue for complex WSN (Wireless Sensor Network). Most of complex WSN employ the sleep mode to reduce the energy dissipation. However, it should cause the reduction of sensing coverage. This paper presents new wake-up algorithm for reducing energy consumption in complex WSN. The proposed wake-up algorithm is devised using geometric probability. It determined which node will be waked-up among the nodes having overlapped sensing coverage. The only one sensor node will be waked-up and it is ready to sense the event occurred uniformly. The simulation results show that the lifetime is increased by 15% and the sensing coverage is increased by 20% compared to the other scheduling methods. Consequently, the proposed wake-up algorithm can eliminate the power dissipation in the overlapped sensing coverage. Thus, it can be applicable for the various WSN suffering from the limited power supply.

Instruction-level Power Model for Asynchronous Processor, A8051

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

Implementation of a Tree-Type Systolic Array BCH Encoder

BCH codes are one of the most widely used error correcting codes for the detection and correction of random errors in the modern digital communication systems. The conventional bit serial BCH cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. In order to prove the efficiency of the proposed algorithm, the throughput and the area overhead was compared with its counterparts. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

A Web-based Realtime Monitoring System for Photobioreactor

This paper presents a web-based real-time monitoring system for a photobioreactor using an WiFi wireless network. An WiFi interface can support high speed data transfer, up to 11Mbps and it can be compatible with commercial wireless LAN environment. Thus, the proposed cell culture based on WiFi network can be easily applied to the reconfigurable system and real-time monitoring system. In this paper, we integrate the commercial WiFi module to the various bio-sensors and sensor control board to configure the wireless network. After we evaluate application S/W for monitoring the environment within incubator, we verify the proposed sensor networks for a cell culture system and its monitoring system. This result can be applicable for various bio-applications that require the network configuration and real-time monitoring system.

Alleviating Light Leakage in LCDs via Diverse Modifications of Polarizer Film

Alleviating Light Leakage in LCDs via Diverse Modifications of Polarizer Film has been retracted atn the request of the authors.