Kyoung-Rok Cho

Motion Compensated Frame Rate Up-Conversion Using Extended Bilateral Motion Estimation

This paper presents a motion compensated frame rate up-conversion algorithm that uses the expanded range of the motion trajectory to enhance the accuracy of motion estimation. In the proposed algorithm, an adaptive motion vector refinement is also proposed to correct false motion vectors. In addition, a recursive motion vector smoothing is proposed to smooth motion vectors considering true neighboring motion vectors only. Finally, we propose the weighted index-based bidirectional motion compensated interpolation to reduce artifacts. In the experiments using benchmark test sequences, the proposed algorithm improves the average PSNR of interpolated frames by up to 4.84 dB, when compared to the conventional algorithm.

Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation

The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.

An Analytical Approach for Memristive Nanoarchitectures

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique I-V characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper, our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and, hence, provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.

A novel CMOS operational transconductance amplifier based on a mobility compensation technique

This brief describes a new linear operational transconductance amplifier (OTA) and its application to a ninth-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation circuit which combines the transistors operating in the triode and the subthreshold regions. The proposed technique enhances the linearity of the transconductance without loss of the input swing range. The proposed OTA shows /spl plusmn/0.5% Gm variation and the total harmonic distortion of less than - 60-dB over the input range of /spl plusmn/0.8-V. The ninth-order Bessel filter employing the proposed OTA has been implemented in a 0.35-/spl mu/m n-well CMOS process under 3.3-V supply voltage. It shows the cutoff frequency of 8 MHz and the power consumption of 65 mW.

High dynamic range CMOS image sensor with conditional reset

In this paper, we propose a new image pixel structure for high dynamic range operation, which is based on a multiple sampling scheme and conditional reset circuits. To expand the dynamic range of the sensor, the output of the pixel is sampled multiple times in an integration time. In each sampling, the output of the pixel is compared with a reference voltage, and the result of this comparison activates the conditional reset circuit. The times of conditional reset during the integration contribute to the increase of the dynamic range of the sensor. Dynamic range can be increased to N, where N is the sampling times in an integration time. The test chip was fabricated with a 0.65-/spl mu/m CMOS technology (2-P, 2-M).

Modeling and analysis of the system bus latency on the SoC platform

In the SoC, the system bus makes a bottleneck for data communication in high speed on a chip. In addition, the system allows multiple bus layers for efficient management of the bus resources on a SoC. In this paper, we present a latency model of the shared bus connecting multiple IPs. Using the latency model, we analyzed the latencies of the system bus on a SoC to get a throughput needed for the system. This result is used as a criterion for setting optimal bus architecture for a specific SoC design. We get latencies for examples MPEG and USB 2.0 using the proposed latency model and compare with the simulation result from MaxSim tools. As a result, the accuracy of the latency model for a single layer and multiple layers is over 96% and 85%, respectively.

Design of a 32-bit fully asynchronous microprocessor (FAM)

The authors describe a 32-b fully asynchronous microprocessor (FAM) with the four-stage pipeline based on a reduced instruction set computing (RISC)-like architecture. Issues relevant to the processor such as design of the self-timed data path, the asynchronous controller and interconnection circuits are discussed. The FAM showed an average operation speed of 3.5 ns for each instruction on 0.5- mu m CMOS technology. Simulation results are included using parameters extracted from the layout.<<ETX>>

Fabrication and modeling of Ag/TiO 2 /ITO memristor

The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in modeling, characterization, and measurements for Memristor-MOS (M2) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M2 circuit performance. In this paper, memristive behavior of titanium dioxide (TiO2) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.

Implementation of high-speed SHA-1 architecture

This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118MHz allows a data throughput rate of 5.9Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data.