Jean Belzile

Bidirectional breadth-first algorithms for the decoding of convolutional codes

Bidirectional multiple-path tree searching algorithms for the decoding of convolutional codes are presented. These suboptimal coding algorithms use a multiple-path breadth-first bidirectional tree exploration procedure and long-memory convolution codes. It is shown that, compared to the usual M-algorithm, the bidirectional exploration considerably reduces the bit error propagation due to correct path loss. Computer simulations using rate-1/2 codes over binary symmetric channels are used to analyze the effect of the number of path extensions, code memory, and frame length on the bit error probability. The results show that with a bit error probability of 10/sup -5/, coding gains on the order of 2 dB over the M-algorithm and 1 dB over a Viterbi decoder of equivalent complexity can be achieved. >

A simple and fast carrier recovery algorithm for high-order QAM

We propose a new carrier recovery algorithm for high-order quadrature amplitude modulation (QAM). The proposed solution relies on two phase detectors, combined with a novel track and hold algorithm for faster frequency acquisition. Compared to previous works, a tenfold improvement or better is achieved in terms of acquisition speed, while keeping a low residual phase noise.

Blind decision feedback equalizer based on high order MCMA

In this paper we propose a blind adaptive algorithm for the decision feedback equalizer based on high order MCMA (modified constant modulus algorithm) and decision directed adaptation. The originality of the proposed method is that the feedforward and the feedback filters are adjusted simultaneously by using the high order MCMA algorithm and by switching to the decision directed mode when the equalized symbols are in the convergence zones. This method reduces the propagation of error caused by the DFE structure. The mean square error (MSE) between the transmitted symbols and the equalized symbols is computed as performance metric. The proposed method is compared to the classic DFE based on second order MCMA. For all simulations, the ensemble-averaged MSE is obtained from 100 Monte Carlo runs. The obtained result show that the proposed method performs well for high constellations in the presence of Gaussian noise, comparatively with other methods.

Frequency domain filter using an accurate reconfigurable FFT/IFFT core

As the time response for a given filter increases, frequency-domain implementation becomes attractive from a hardware resources point of view. This paper shows that for practical cases, the crossover between frequency-domain and time-domain implementations may be as low as 8 complex coefficients. The focus is on the design of efficient and reconfigurable FPGA implementations of frequency-domain filters. The filter size, binary word length of input, output, and coefficients are all configurable. Internal bus word lengths are also parameterized to control result accuracy. For example, a SQNR of 55 dB can be obtained for a 32 coefficient raised cosine filter of /spl alpha/=0.22 with 5 bit input and 12 bit output. This is compared to a maximum of 48 dB for a comparable FIR.

Asynchronous component implementation methodology for GALS design in FPGAs

A methodology for implementing GALS design in conventional FPGAs using existing tools is presented. The goals were to define the minimal set of basic asynchronous components, to examine the methodology of their implementation and to establish the design constraints and limitations of such circuits. Simulation results confirm that GALS designs implemented using the Look-Up Table or the Flip-Flop with Place & Route tools and asynchronous components such as the delay element, the Muller-C element or the arbiter are supported by conventional synchronous FPGAs as long as these designs are implemented within suitable constraints and operated within circuit limitations.

Adaptive M-QAM scheme and unbiased MMSE-DFE receiver

In this paper, an adaptive quadrature amplitude modulation (AQAM) scheme for an equalized system over a selective channel is investigated. To reduce intersymbol inter- ference (ISI), a minimum-mean-squared-error decision feedback equalizer (MMSE-DFE) with an unbiased decision rule is used. In order to select the appropriate modulation mode, the receiver estimates the MSE at the equalizer output. The estimated MSE is then sent back to the transmitter which adjusts the modulation level. A reliable feedback link between the receiver and the transmitter is required to achieve good performances.

On a complete simulation model for the design of high-speed digital radios

This paper describes a complete digital radio system model which takes into account the effects of most degradations due to channel conditions and equipment imperfections. System parameters which are taken into consideration include, but are not limited to, the following: modulator imbalance, filter frequency responses, power amplifier nonlinearities, carrier and symbol timing recovery loops, and synthesizer phase noise. The parameters for each module in the radio can be varied, and the end-to-end performance computed. Furthermore, a novel semianalytic method is developed for the purpose of speeding up the simulation leading to the calculation of the bit error rate (BER) versus E/sub b//N/sub o/ for the radio model. This novel technique, when compared with classical semianalytic methods, provides 1 dB improvement in the accuracy of the simulation results. The model accurately predicts the radio performance as measured by BER versus E/sub b//N/sub o/, dispersive fade margin, transmitted frequency spectrum, and transient acquisition responses. Simulation results for 16 QAM and OQPSK systems were compared to measurements on two physical radios. The accuracy of the simulation results was found to be within 0.1 dB in E/sub b//N/sub o/ at a BER of 10/sup -6/ without the RF portions and between 0.2 and 0.45 dB for a complete radio system.

Bounds on the performance of partial selection networks

The evaluation of the performance of partial selection networks which select a set of M elements from a set of N inputs is addressed. The partial selection problem occurs when dealing with non-exhaustive multi-path breadth-first searches, like in the M algorithm or the bidirectional algorithm. These algorithms are used in the decoding of convolutional codes. The paper presents a set of bounds to evaluate the quality of regular, Delta class, networks of depth 1gN and width N/2, with respect to their selection capabilities. The results from the bounds are compared to Monte Carlo simulations of the selection capabilities of the Banyan and Alekseyev networks. Finally, the performance degradation associated with the use of these networks on the performance of a bidirectional decoder is presented. In particular, the authors show that even with imperfect selection, the bidirectional decoder can outperform a Viterbi decoder of comparable complexity. >

Reconfigurable and efficient FFT/IFFT architecture

Hardware or firmware implementations of fast Fourier transforms are found in many digital signal processing applications. However, most commercially available FFT/IFFT firmware cores lack reconfigurability, thus impeding reuse and increasing cost, design time, etc. The proposed FFT/IFFT core addresses those issues. It is parameterizable, flexible, and scalable at the design time. The resources needed for an FPGA implementation are comparable to the ones required by non-reconfigurable cores and significantly fewer than those required by available reconfigurable cores. Finally, the design allows real-time processing of a serial input signal, while adding minimal processing latency and optimizing memory usage.

Towards a Coherent Framework for Automated RF Front-End Design Using Hardware Abstraction

Although RF front ends represent a very important part in communication equipments, relatively small efforts have been made in order to automate their design process and, consequently, their hardware abstraction. By contrast, baseband designers routinely make use of hardware abstraction tools and techniques and use synthesis approaches to generate complex functionalities on various hardware platforms saving time and money in the process. To bridge this gap between the baseband and RF, a framework for the RF design cycle that incorporates functional description and hardware abstraction with circuit synthesis in an automated process is needed. In this paper, we propose such a framework and outline its main building blocks. The key concept in the proposed framework is a new unified matrix representation of the electrical behavior of RF components, dubbed the Q-matrix. The foundations and details of this Q-matrix representation are presented.