Jean Calvignac

IBM PowerNP network processor: Hardware, software, and applications

Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates. As a result, more services will have to be performed at the edges, on behalf of both the core and the end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas, in the past, network equipment was based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. This paper provides an overview of the IBM PowerNPTM NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software make it well suited for a wide range of networking applications.

Search engine implications for network processor efficiency

Network processors are programmable devices with special architectural features that are optimized to perform packet forwarding decisions. Those decisions are often based on data accessed from various table structures. Access to these structures typically requires one of several search methods, each of which consists of multiple individual memory accesses, leading to significant latency to complete the process. One of the architectural features of network processors is multithreading of each processing element in order to hide the effects of these long latency searches. Hardware search engines can significantly reduce the latency of such searches, and are shown to have a significant impact on the number of threads required in each processing element.