Jean-Francois Cote

An automated, complete, structural test solution for SERDES

Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and inter-board data transmission technique. Signal integrity is the primary factor determining its bit error rate, typically less than 10/sup -12/, so the primary production test challenges are testing picosecond jitter and the signal eye opening. Off-chip jitter and rise/fall time measurements are limited by hardware complexity, access, bandwidth, and noise. Published on-chip measurement techniques are limited by delay line jitter. This paper presents a new jitter test technique that has been demonstrated on an FPGA to achieve less than 1 ps RMS self-jitter, and a new signal eye test that has unlimited bandwidth; neither test uses high speed circuitry. The all-digital technique uses the receiver itself to demodulate the signal jitter to a low-speed bit stream that is analyzed by a single-clock domain, synthesizable circuit. This is combined with logic BIST and 1149.6 boundary scan to completely test an IC.

An embedded technique for at-speed interconnect testing

A new embedded test technique which provides full at-speed testing of board level interconnect is described. The proposed technique is fully compatible with the IEEE 1149.1 boundary scan standard. The technique extends the standards architecture to provide for synchronized at-speed timing control of the boundary scan cells so that test data can be applied and captured across the interconnect at system speeds.

IEEE P1687: Toward Standardized Access of Embedded Instrumentation

The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware interface scheme are all taking shape, but still have many details to complete. Since this is a snapshot taken during the standard development process, the final form of the draft standard may differ from what is described here; any feedback to the working group is welcome

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

The BurstModetrade test clocking methodology, first presented in, is improved to handle circuits with synchronous clocks of different frequencies. An on-chip clock controller allows to select a large number of clock waveforms necessary to test synchronous cross-domain paths at-speed and control supply voltage variations. The methodology is applicable to both ATPG and BIST and only requires combinational analysis tools. The methodology is applied to a large circuit to adjust power supply margins of an at-speed BIST test.

Streaming fast access to ADCs and DACs for mixed-signal ATPG

An analog test bus and serial digital access to ADC and DAC parallel ports are two widely used analog DFT techniques. Unfortunately, they cannot be described in a standard way that could facilitate automatic test pattern generation (ATPG). Furthermore, serially accessing an ADC/DAC is typically too inefficient for periodic sampling for various reasons, but mostly because of the capture/update-then-shift sequence used in IEEE 1149.1, 1500, and 1687. This paper shows that if a small amount of digital circuitry is added to each accessed ADC/DAC parallel port, they could be described in IEEE 1687 instrument connection language (ICL) to facilitate optimally efficient streaming access to the parallel ports. Furthermore, this could be automated by adding our proposed “iStream” as a new 1687 procedural description language (PDL) command. We provide examples of how it would be used, along with evidence to show it can provide more efficient (up to 2X, or more) serial access rate to ADCs and DACs than previous automatable approaches.