Benoit Nadeau-Dostie

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

The BurstModetrade test clocking methodology, first presented in, is improved to handle circuits with synchronous clocks of different frequencies. An on-chip clock controller allows to select a large number of clock waveforms necessary to test synchronous cross-domain paths at-speed and control supply voltage variations. The methodology is applicable to both ATPG and BIST and only requires combinational analysis tools. The methodology is applied to a large circuit to adjust power supply margins of an at-speed BIST test.

Improved Core Isolation and Access for Hierarchical Embedded Test

IEEE Std 1500 enables automation and hence allows for easier and faster integration of embedded cores into an SoC. This article describes an automated test development system based on the concept of embedded test.

A BIST algorithm for bit/group write enable faults in SRAMs

The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories.