Jean Godin

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ges50-GHz- clock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD- HBT equations. These large signal models have allowed the design of 50-GHz clocked 50 G Decision and 100 G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

Cost-optimized 6.3 Tbit/s-capacity terrestrial link over 17 /spl times/ 100 km using phase-shaped binary transmission in a conventional all-EDFA SMF-based system

We demonstrate the feasibility of 6.3 Tbit/s capacity over 17 /spl times/ 100 km using well-proven all-erbium-doped fiber amplifier technology over a typical ultra-long haul link based on standard fiber. This experiment emphasizes the advantages of our modulation format, namely phase-shaped binary transmission.

MSI InP/InGaAs DHBT technology: beyond 40 Gbit/s circuits

We present current results obtained on IC-oriented OPTO+ InP DHBT lab technology. Transistors with 180/210 GHz F/sub t//F/sub max/, current gain of 50 and BV/sub ce0/=7V are currently fabricated with >99% fabrication yield. Uniformity measurements show a standard deviation on F/sub t/ and F/sub max/ lower than 2% and lower than 5% on all investigated parameters. In a second part DHBT-specific modelling issues are discussed. A 68 Gbit/s selector has been obtained and a 40 Gbit/s master-slave D-type flip-flop (MS-DFF) has been reproducibly fabricated with >50% functional yield using this technology.

InP DHBT technology and design methodology for high-bit-rate optical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions.

DC-100-GHz frequency doublers in InP DHBT technology

Broad-band monolithic integrated active frequency doublers operating in dc-100-GHz frequency range are presented. Circuits are fabricated in a self-aligned InP double heterojunction bipolar transistor process. Three integrated doubler versions have been designed. Inductive peaking and active splitting effects are quantified and compared. Circuit measurements give sinusoidal output waveform at 100 GHz with an rms timing jitter of 400 fs. Circuits have a maximum conversion gain of +1 dB at 60 GHz. the fundamental suppression is better than 24 dB in the whole frequency range.

InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations.

A 1-GSample/s, 15-GHz Input Bandwidth Master–Slave Track-and-Hold Amplifier in InP DHBT Technology

A fully differential master-slave track-and-hold amplifier is designed and fabricated in a 210-GHz-f T InP DHBT process. Input bandwidth of 15 GHz, total harmonic distortion lower than -39 dB and a third harmonic rejection greater than 45 dB are measured for 1 GSample/s and 4 dBm single-ended input signal. Time domain measurements demonstrate the performances of dual track-and-hold amplifier for Nyquist, over-sampling and sub-sampling conditions. Design tradeoff for master and slave blocks are presented. Experimental results obtained for different feed-through capacitors (C FF) show the effects of C FF on bandwidth and isolation.

A Large-Swing 112-Gb/s Selector-Driver Based on a Differential Distributed Amplifier in InP DHBT Technology

We report a 2:1 selector-driver based on a differential distributed amplifier realized in a 0.7-μ m indium phosphide double heterojunction bipolar transistor technology. From transistors reaching fT/fmax of 320/380 GHz and a breakdown voltage (BVCEO) of 4.5 V, the selector-driver provides a differential eye amplitude of up to 6.2 and 5.9 VPP at up to 100 and 112 Gb/s, respectively, for a power consumption of 3.8 W, achieving a record swing-speed product of 620 and 660 VGb/s, respectively.

A broad-band active frequency doubler operating up to 120 GHz

A broad-band monolithic integrated active frequency doubler operating in DC-120 GHz frequency range is presented and compared with several previous versions. The circuit is fabricated in a self-aligned InP DHBT process. Circuit measurements show sinusoidal output waveform at 120 GHz. For -8 dBm input power, the doubler has a maximum conversion gain of -0.25 dB at 50 GHz due to a peaking inductor on the doubler output.

InP HBT driver circuit optimization for high-speed ETDM transmission

The design of high-speed circuits and optimization of function of technological and geometrical parameters are presented. Various modeling aspects are discussed, such as model accuracy for InP heterojunction bipolar transistor and modeling with technological and geometrical parameters. MUX-driver design and optimization for 40-Gb/s ETDM transmission is presented. The impact of collector thickness (W/sub c/) on driver performances is evaluated and assessed by circuit fabrication and measurements. Results of 40-Gb/s electrical measurements and optical experiment with realized MUX-driver module are presented.