Jean Laconte

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

SOI CMOS compatible low-power microheater optimization for the fabrication of smart gas sensors

In this paper, an original design of a polysilicon loop-shaped microheater on a 1-/spl mu/m thin-stacked dielectric membrane is presented. This design ensures high thermal uniformity and insulation and very low power consumption (20 mW for heating at 400/spl deg/C). Moreover, the use of completely CMOS compatible tetramethyl ammonium hydroxide-based bulk-micromachining techniques allows an easy, smart gas sensor integration in SOI-CMOS technology.

High-sensitivity capacitive humidity sensor using 3-layer patterned polyimide sensing film

This paper investigates novel isolation and patterning schemes to increase the sensitivity of a capacitive humidity sensor based on a polyimide sensitive layer. We obtained an optimum sensitivity of 23% using aluminum interdigitated electrodes with fingers of 1 nm width separated by 1 pm, deposited on a first insulating polyimide layer and covered by two more polyimide layers whose upper one features a regular array of holes to increase the active surface area. A mathematical model was developed to optimize the sensitivity regarding water absorption factor, electrodes design and ratio between active and parasitic capacitances. The process was optimized to be fully compatible with usual CMOS-IC processes in order to finally be able to fabricate a humidity smart sensor.

Low-cost optical instrumentation for thermal characterization of MEMS

A low-cost, non-destructive and flexible technique based on thermoreflectometry is presented in this paper to map the temperature of running devices integrated on a silicon chip. The analysed device is a micromachined gas sensor using silicon-on-insulator technology (SOI). The interests and limitations of the proposed optical technique are described and compared with commonly used methods in microelectronics. Moreover, experimental results of thermal mapping for micromachined gas sensors are also compared with numerical simulations. From the measured temperature distribution over the entire active area of micromachined gas sensors, optimized designs can be proposed for avoiding hot spots that degrade the performance of the integrated gas sensors.

Capacitive humidity sensor using a polyimide sensing film

This paper investigates novel isolation and patterning schemes to increase the sensitivity of a capacitive humidity sensor based on a polyimide sensitive layer. We obtained an optimum sensitivity of 23% using aluminum interdigitated electrodes with fingers of 1 /spl mu/m width separated by 1 /spl mu/m, deposited on a first insulating polyimide layer and covered by two more polyimide layers whose upper one features a regular array of holes to increase the active surface area. A mathematical model was developed to optimize its sensitivity regarding water absorption factor, electrodes design and ratio between active and parasitic capacitances. Its process was optimized to be fully compatible with usual CMOS-IC processes in order to finally be able to fabricate a humidity smart sensor.

Intelligent SOI CMOS integrated circuits and sensors for heterogeneous environments and applications

In this paper, we demonstrate how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components. High-temperature and low-voltage examples are discussed.

SOI CMOS compatible low-power microheater optimization and fabrication for smart gas sensor implementations

In this paper, an original design of a polysilicon loop-shaped microheater on a thin stacked dielectric membrane is presented. This design ensures high thermal uniformity and insulation (20.000/spl deg/C/W) and very low power consumption (20 mW for heating at 400/spl deg/C). Moreover, the use of completely CMOS compatible TMAH-based bulk-micromachining techniques allows an easy smart gas sensor integration in SOI-CMOS technology.

Fully CMOS-SOI compatible low-power directional flow sensor

The paper reports an improved low cost directional flow sensor, fully compatible with IC-CMOS SOI (silicon-on-insulator) processes, with fair sensitivity and short response time on a large airflow rate range (from 0 to 8 m/s) at a very low consumption (15 mW). Many different sensing principles can be found in the literature and impose a difficult choice between low power consumption, high airflow rate range, sufficient flow rate sensitivity and compatibility with IC processes. Our sensor challenges most recent realizations by providing attractive trade-offs between these parameters for a large range of applications.

Fully CMOS compatible low-power microheater

An original design of a polysilicon loop-shaped microheater on a thin stacked dielectric membrane is presented. This design ensures high thermal uniformity and insulation (20.000 degree(s)C/W) and very low power consumption (20 mW for heating at 400 degree(s)C). Moreover, the use of CMOS-IC compatible TMAH-based bulk-micromachining techniques will allow easy and low cost gas sensor integration.

Advantages of p ++ polysilicon etch stop layer versus p ++ silicon

Boron highly doped silicon is now widely used as etch stop layer in MicroElectroMechanical Systems (MEMS) devices fabrication. The present paper shows the advantages of replacing the p++ Si etch stop layer by a p++ polysilicon layer. The etch rate of Tetramethylammoniunhydroxide (TMAH) is measured for LPCVD polysilicon and silicon doped with Boron at concentrations from 8.1018 up to 4.1020 atoms/cm3 which is the Boron solubility limit into Si. TMAH etch being often used during back-end process, selectivity to aluminium is usually needed. The etch selectivity of various TMAH solutions for p++ Si, p++ Poly and aluminium have been measured, from 25 % to 5 % TMAH pure and mixed with silicon powder and ammonium persulfate. Contrarily to silicon, polysilicon is etched isotropically in TMAH solution which constitutes a great advantage when cavities with vertical walls have to be opened. Although the polysilicon etch rate is higher than the silicon one, the selectivity (doped/undoped) is the same for the both materials, allowing identical uses. Another great advantage of polysilicon is that it can be deposited at any process step and does not require clever epitaxy steps or wafer bonding as for silicon. The surface roughness of the etched Poly region is considerably decreased with TMAH mixed with silicon powder and ammonium persulfate mixture compared to pure 25 % TMAH solution. The definition of buried masks in polysilicon layer through Boron implant is the main foreseen application. The p++ Poly buried mask brings solutions for the fabrication of self-aligned double gate MOS, microfluidic or optical networks in MEMS field.