Jean-Luc Beuchat

Static and dynamic configurable systems

Field-programmable gate arrays (FPGAs) are large, fast integrated circuits-that can be modified, or configured, almost at any point by the end user. Within the domain of configurable computing, we distinguish between two modes of configurability: static-where the configurable processors configuration string is loaded once at the outset, after which it does not change during execution of the task at hand, and dynamic-where the processors configuration may change at any moment. This paper describes four applications in the domain of configurable computing, considering both static and dynamic systems, including: SPYDER (a reconfigurable processor development system), RENCO (a reconfigurable network computer), Firefly (an evolving machine), and the BioWatch (a self-repairing watch). While static configurability mainly aims at attaining the classical computing goal of improving performance, dynamic configurability might bring about an entirely new breed of hardware devices-ones that are able to adapt within dynamic environments.

Hardware Reconfigurable Neural Networks

This paper presents the concept of reconfigurable systems using the example of a digital hardware implementation of neural networks, as well as RENCO, a platform very well-suited for the prototyping of such systems. RENCO is a network computer containing a reconfigurable part composed of four Flex10K FPGAs from Altera (10K130 or 1OK250).

Von Neumann's 29-state cellular automaton: a hardware implementation

In the early 1950s, John von Neumann designed a cellular automaton implementing a universal self-replicating structure. More than 40 years after his death, the first hardware implementation of von Neumanns transition rule is presented. Unfortunately, this implementation only allows small systems to be realized, and not the complete structure, which would require 100000-200000 cells, according to some estimations. A logic circuit which implements the transition rule and represents a single cell of the array has been developed. The applications of this implementation lie mainly in the pedagogical domain. It can be used as a demonstration tool for courses on cellular automata.

RENCO: a reconfigurable network computer

RENCO is a reconfigurable network computer based on a Motorola 68360 processor for the conventional part, and four Altera Flex 10K130 or 10K250 FPGAs for the reconfigurable part. Therefore, the user has at his/her disposal up to one million programmable logic gates for executing his/her applications in a custom-made processor. RENCO runs a real-time operating system and a Java virtual machine.

A Reconfigurable Neuroprocessor with On-chip Pruning

The appearance of fast reconfigurable FPGA circuits brings about new paths for the design of neuroprocessors. A learning algorithm is divided into different steps that are associated with specific FPGA configurations. The training process then consists of alternating computing and reconfiguration stages. Such a method leads to an optimal use of hardware resources. This new method is applied to the design of a neuroprocessor implementing multilayer perceptrons with on-chip training and pruning. All arithmetic operations are carried out with fixed-point numbers. The first step of our work is the simulation of limited precision training and pruning algorithms. Our experiments demonstrate that this representation is well suited for this task. This paper also presents the principles of our hardware implementation, focusing in particular on the pruning mechanisms.

Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementation

Artificial neural networks can solve complex problems such as time series prediction, handwritten pattern recognition or speech processing. Though software simulations are essential when one sets about to study a new algorithm, they cannot always fulfill real-time criteria required by some practical applications. Consequently, hardware implementations are of crucial import.

From configurable circuits to bio-inspired systems

Field-programmable gate arrays (FPGAs) are large, fast integrated circuits — that can be modified, or configured, almost at any point by the end user. Within the domain of configurable computing we distinguish between two modes of configurability: static—where the configurable processor’ s configuration string is loaded once at the outset, after which it does not change during execution of the task at hand, and dynamic— where the processor’ s configuration may change at any moment. This chapter describes six applications in the domain of configurable computing, considering both static and dynamic systems, including: SPYDER (a reconfigurable processor development system), RENCO (a reconfigurable network computer), an FPGA-based backpropagation neural network, Firefly (an evolving machine), BioWatch (a self- repairing watch), and FAST (a neural network with a flexible, adaptable-size topology). Moreover, we argue that the rise of configurable computing requires a fundamental change in the engineering curriculum, toward which end we present the LABOMAT board, developed for use by students in hardware design courses. While static configurability mainly aims at attaining the classical computing goal of improving performance, dynamic configurability might bring about an entirely new breed of hardware devices — ones that are able to adapt within dynamic environments.1

An On-Line Arithmetic-Based Reconfigurable Neuroprocessor

Artificial neural networks can solve complex problems such as time series prediction, handwritten pattern recognition or speech processing. Though software simulations are essential when one sets about to study a new algorithm, they cannot always fulfill real-time criteria required by some practical applications. Consequently, hardware implementations are of crucial import. The appearance of fast reconfigurable FPGA circuits brings about new paths for the design of neuroprocessors. All arithmetic operations are carried out with on-line operators. This short paper briefly describes reconfigurable FPGA-based neural networks and gives an introduction to on-line arithmetic.