Arnaud Tisserand

Multiplication in GF(2m): area and time dependency/efficiency/complexity analysis.

Abstract Efficient arithmetic units are crucial for cryptographic hardware design. The cryptographic systems are based on mathematical theories thus they strongly depend on the performance of the arithmetic units comprising them. If the arithmetic operator does not take a considerable amount of resources or is time non efficient it negatively impacts the performance of the whole cryptosystem. This work is intended to analyse the hardware possibilities of the algorithms performing multiplication in finite field extensions GF(2 m ). Such multipliers are used in Elliptic Curve Cryptography (ECC) applications. There are only two operations defined in the field: addition and multiplication. Addition is considered as a trivial operation - it is a simple bitwise XOR. On the other hand multiplication in the field is a very complex operation. To conform to the requirements of ECC systems it should be fast, area efficient and what is the most important perform multiplication of large numbers (100 - 600 bits). The paper presents analysis of GF(2 m ) two-step modular multiplication algorithms. It considers classical (standard, school-book) multiplication, matrix-vector approach algorithm and Karatsuba-Ofman algorithm, exploring thoroughly their advantages and disadvantages.

Analysis of GF (2233) multipliers regarding Elliptic Curve Cryptosystem applications.

The paper presents overview of the most interesting GF (2^m) algorithms and proposes efficient hardware solutions applicable to elliptic curve cryptosystems. It focuses on fields of size m = 233, one of the sizes recommended by NIST (National Institute of Standards and Technology). We perform analysis of most popular algorithms used for multiplication over finite fields; suggest efficient hardware solutions and point advantages and disadvantages of each algorithm. The article overviews and compares classic, Mastrovito and Montgomery multipliers. Hardware solutions presented here, implement their modified versions to gain on efficiency of the solutions. Moreover we try to present a fair comparison with existing solutions. It is hard to compare different hardware finite field multipliers designs due to the fact that the most important improvements are described only theoretically. The designs presented here are targeted to FPGA devices.