Jean Luc Philippe

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations

Early performance feedback and design space exploration of complete field-programmable gate array (FPGA) designs are still time consuming tasks. This paper proposes an original methodology based on estimations to reduce the impact on design time. It promotes a hierarchical exploration to mitigate the complexity of the exploration process. Therefore, this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many register-transfer level (RTL) implementations to prune the design space. Two main steps compose the flow: 1) a structural exploration step defines several RTL implementations, and 2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, it focuses on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement, or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area/delay tradeoffs. The paper also do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth, or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e., an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a two-dimensional Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations

Fast prototyping of reconfigurable architectures from a C program

Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural estimation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the target reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex 10K, Apex) components for a 2D DWT and a speech coder lead to an average error of about 10% for temporal values and 18% for area estimations.

Generic design space exploration for reconfigurable architectures

We propose in this paper an original design space exploration method for reconfigurable architectures adapted to fine and coarse grain resources. The exploration flow deals with communication hierarchical distribution and processing resources use rate for the architecture under exploration. With this information, designer can explore the architectural design space to define a power-efficient architecture. Exploration results for image computing and cryptography applications are provided to demonstrate the efficiency of the method.

A component based approach for the design of FMS control and supervision

This paper deals with the reconfiguration of flexible manufacturing systems. It presents a methodology that addresses the whole reaction loop toward failures. The major key point is the component notion that provides an easy way to get several models used in the monitoring supervision and control modules. A component is a reusable element that is composed of several views including partial models. It is formalized referring to the notion of operations and described using UML standard. Three views are delineated in this paper: monitoring view, supervision view and control view. Workshop models are built from these three views. The computation and the interactions of these models enable to get a relevant reaction for the reconfiguration process. Works concerning the detection, identification of down operations, the decision of a new configuration and the updating of control are presented.

Design of a multimedia processor based on metrics computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on todays processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility.

Targeting tiled architectures in design exploration

Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under development at LESTER-UBS. The tool allows various reconfigurable architectures to be compared for different applications and sets of constraints. One of the challenges of the tool is the ability to estimate interconnect costs at a high level of abstraction. This project explores the use of the Adaptive System on a Chip (aSoC) tiled architecture, developed at UMASS as a target architecture for design exploration. aSoC provides an important capability to the LESTER tool by allowing interconnect costs to be modeled very early in the design process by partitioning and placing each portion of the computation into a square tile on a 2D grid. aSoC is primarily an interconnect architecture, based on static scheduling of virtual interconnects onto a highly characterized and regular physical interconnect fabric. aSoC supports a wide variety of cores, including dedicated, hardware programmable and software programmable thus allowing a wide range of design exploration.

A Modeling Method for Reconfigurable Architectures

Field Programmable Gate Arrays (FPGAs) are now integrated in complex electronic systems and are not only used during the prototyping phases. Moreover, their application space is getting larger thanks to their flexibility, which is obtained through the reconfiguration. For these reasons component industries are proposing more and more FPGAs with different architectures, sizes, capabilities. Designers are then faced to a larger choice in the design space but they do not have any tool to efficiently compare different reconfigurable architectures. In this paper a reconfigurable architecture zodeling method is presented. The proposed model is applied to a domain representative component in order to show its ability to describe a complex architecture. The modeling method, which is based on a functional view, is able to describe complex, heterogeneous and multi-granularity architectures. In future works the modeling method will be combined to a generic FPGA architecture estimation tool.

System Level Design Space Exploration for Multiprocessor System on Chip

Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods in order to meet future design constraints. We believe one solution is to add a new design exploration step above current methods. This extension corresponds to an abstraction rising to provide designer with a restricted design space. We propose in this work to enrich the classical exploration approaches by a pre-exploration step which reduces the architecture design space. This new step (i) simplifies (ii) performs and (iii) makes possible, for a complex application the architecture exploration for future tera-scale multiprocessor-based systems. This method drastically reduces the architecture space at a higher level of the design flow which mitigates the codesign complexity and enables the designer to explore a large set of architectures.

Generation of control for conveying systems based on component approach

This paper proposes a methodology for automatic control generation of conveying systems. Its purpose is to automate the development of discrete control programs in order to reduce costs. It is based on components to model controlled conveying systems. A component is a reusable element that includes several views including partial models. It is formalized referring to the notion of operations. Four views are delineated in this paper: operating part view, constraints view, topological view and control view. The control model of the workshop is built on these views. The procedure uses these partial models and refers to model transformation to provide an easy way to obtain source code compatible with the IEC 61131-3 standard. Tools allowing to implement the methodology are also presented, along with some applications.

Using model engineering for the criticality analysis of reconfigurable manufacturing systems architectures

Reconfigurable Manufacturing Systems (RMS) have the ability to evolve in response to a change in their environment or a modification of their composition (after a failure of one of its parts for instance). In the first part, this paper introduces a model for the representation of these systems that takes into account the concepts of architecture (the components of the system) and configuration (the relations between the components) and separates the logical part constituted by products from the physical part constituted by resources. A UML representation is proposed for this model. The second part of this article deals with the concept of tolerance and proposes automatic evaluation from the UML representation of the architecture. More precisely, architecture part of the model is derived through model transformation into an analysis model for evaluating the capability of the system to provide its functions in spite of the failure of one of its elements.