Jean-Marie Gaultier

Conception of UHF voltage multiplier for RFID circuit

This paper presents a study and an optimization of a diode voltage multiplier including antenna matching problems. Results on this multiplier designed in a 0.18mum CMOS process are shown. It can power a RFID integrated circuit at a distance of 10 m with an efficiency of 30%. In this paper a simple analytical model of the complete tag including antenna and chip is presented. This model allows explaining results on crucial points of voltage multiplier design method. A test chip is designed and realized in collaboration with ST Microelectronics. Many measures are then realized and present good agreement with simulation results