Francois Tailliet

Characterization of an n-p-n structure under ESD stress and proposed electrical model

The real-time electrical behavior of an n-p-n electrostatic discharge (ESD) protection structure is studied. The fabrication process is a classical CMOS n-well. Measurement difficulties are described, and quantitative results are emphasized. Successive conduction mechanisms for both polarities, such as diffusion delays and thermal runaway, are demonstrated by experiments. A simple qualitative model that agrees with the measurements is proposed. The results also explain many in-circuit ESD failures due to unwanted n-p-n structures and allow the creation and justification of efficient ESD-protective design rules. >