Jean-Paul Heron

Implementation of the 2D DCT using a Xilinx XC6264 FPGA

This paper presents a novel FPGA implementation of a two dimensional (8/spl times/8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.

Applying an XC6200 to real-time image processing

This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve high-performance custom-computing implementation.

Fast partial reconfiguration for FCCMs

The emergence of new FPGA families such as the Xilinx 6200 FPGA family and the Atmel 40000 series has been an important development in the FPGAs for Custom Computing Machines (FCCMs). These devices have number of appealing features when compared to other technologies such as the Xilinx 4000 series SRAM technology. These can be characterised as follows: faster reconfiguration (typically m/spl mu/ s or /spl mu/s), support for partial reconfiguration, dedicated microprocessor interface. An approach for run-time reconfiguration can be achieved by considering a range of functions collectively and developing the specific circuit architectures for each so that a high degree of commonality exists between them in terms of their structure, wiring and cell function. This is done by representing the functions or algorithms using Signal Flow Graphs (SFGs) and manipulating them to produce similar graphs for different functions. This basic concept can only be exploited through the development of an efficient hardware system. This revolves around the concept of virtual hardware which is integrated within the operating system and is supported by programming languages such as C and C++. The reconfigurable designs which allow partial re-configuration, are stored within a configuration data graph. Whilst this allows the configuration data to be efficiently stored, reconfiguration state graphs are used for high speed reconfiguration. The entire software hardware system for fast partial reconfiguration is illustrated.

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing “design for reconfiguration” where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.

Accelerating run-time reconfiguration on FCCMs

The paper describes the implementation of the arithmetic operations of multiplication, division and square root on a Xilinx XC6200 FPGA. By using a design approach to enhance similarities across circuits, partial reconfiguration has been used to allow reductions in reconfiguration times of up to 75% on trials using the VCC HOTWorks board.

Image compression algorithms using re-configurable logic

The implementation of the 2D discrete cosine transform (DCT) using the Xilinx XC620D re-configurable FPGA technology, is presented. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organisation (distributed arithmetic) and algorithm-to-architecture mappings (parallelism and pipelining). A throughput rate of 1.536/spl times/10/sup 7/ pixels per second for the 2D DCT circuit is achievable (equivalent to processing colour images of VGA resolution (640/spl times/480 pixels) at 25 fps) which is the equivalent of 2 million operations per second. This demonstrates that the XC6254 can produce an order of magnitude speed-up over current microprocessors.

Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA

The adoption of FPGA technology for custom computing and other applications will depend greatly on how efficiently architectures may be implemented. In this paper we investigate architectural strategies for implementing a typical image processing algorithm, in this case, Laplacian convolution, on the Xilinx XC6000 series technology. Three approaches are illustrated and the resulting designs are presented. Discussion for extending this work to operate with a high level design tool currently under development, is also given.

FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)

The implementation of a number of FIR filter structures in the Xilinx XC6200 technology is presented. The designs have been implemented using a combination of IRIS, an architectural synthesis tool and Trianus/Hades a set of integrated tools for implementing algorithms on Custom Computing Machines. The main attraction of this approach is that it allows algorithms to be compiled quickly allowing performance changes to be made at the architectural level in IRIS rather than at the FPGA layout level.

Accelerating run-time reconfiguration on custom computing machines

Custom computers comprising of a host processor and FPGAs have been proposed to accelerate computationally complex problems. Whilst the FPGA implementation might be considerably faster than its microprocessor counterpart, this performance acceleration can be degraded by the time to reconfigure the FPGA hardware.This paper demonstrates a technique for developing circuits that can reduce the reconfiguration overhead. Circuits for three basic arithmetic functions multiplication, division and square root have been developed using the Xilinx XC6200 reconfigurable FPGA family. Reconfiguration times have been measured by downloading the designs to the VCC HOTWorks custom computing board. A reduction in reconfiguration time of up to 75 percent has been demonstrated using this design approach.

Advances in Adaptive Signal Processing: Totally Adaptive Systems

Abstract The design of traditional adaptive systems in signal processing applications has been strongly influenced by the need to provide an efficient implementation. At high bandwidths this has tended to be an ASIC (Application Specific Integrated Circuit). This, together with the need to make adaptation as reliable as possible has led to the use of as much a-priori knowledge as possible in the design. The result is often a non-optimal design. This paper examines an alternative strategy which removes many of the a-priori constraints and targets an implementation based on a real-time reconfigurable hardware platform.