Jean-Philippe Blonde

Quantization problem analysis on ASIC-based direct torque control of an induction machine

Latest developments in digital intelligent motion, as digital signal processors (DSPs), has strongly improved AC motor control performances. Application-specific-integrated circuit (ASIC) technology has changed the need for rapid process and low-cost processor. However, new technological problems appeared, requiring digital properties which need considering, such as quantization, sampling, word length and data types. The authors of this paper propose to study the quantization problems on ASIC-based direct torque control of an induction machine. They present a high level behavior model of the specific circuit and analyze the torque quantization errors. Finally, simulation results illustrate quantization influences on control performances with different data type solutions.

3D Hall probe integrated in 0.35 μm CMOS technology for magnetic field pulses measurements

This paper presents a 3 dimensional magnetometer based on Hall effect sensors integrated without any post processing in a standard low cost 0.35 mum CMOS technology. The system is dedicated to magnetic pulses measurements under a strong static field. Two vertical Hall devices (VHD) are sensitive to the components of the magnetic field oriented in the plane of the chip, while a horizontal Hall device (HHD) is sensitive to the component of the magnetic field orthogonally oriented to the plane of the chip. 3 identical instrumental chains are integrated to perform amplification of the 3 Hall voltages. The system implements a compensation of the static magnetic field and allows to measure magnetic fields pulses with a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth. Pulses are in the range from hundreds of muT to tens of mT in the frequency range from 1 Hz to 10 kHz. The static field is compensated up to 1.5 T. The spatial resolution is 44 mum. The system power consumption has been optimized to 15 mW.

CMOS integrated system for magnetic field monitoring and gradient measurement in MRI environment

This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.

A Vertical Hall Device in Standard Submicron CMOS Technology

In order to lower the short circuit effect due to the measurement contacts, vertical Hall devices (VHD) are generally designed either in bulky N-type silicon or in the deep N-well of high-voltage CMOS technologies. In this last case, VHD can benefit from on chip circuitry for offset and 1/f noise reduction, but HVCMOS remains a costly technology. Recently, using spinning-current, a HVCMOS compatible VHD with a resolution of 76 muT over a 1.6 kHz bandwidth has been demonstrated. The VHD presented here is designed in the shallow N-well of a low cost 0.35 mum standard CMOS technology. Unlike conventional VHD, its measurement contacts are located outside the sensor active area. FEM simulations and experimental results show that the new geometry suppresses the short circuit effect and strongly reduces the intrinsic offset and noise. Thus, without any noise and offset reduction method, this new small VHD (63 mum2) reaches a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth.

Chopper stabilized CMOS integrated front-end for magnetic field measurement

This paper presents an analogue front-end dedicated to magnetic field measurement that is intended to be used in a mixed signal submicron CMOS microsystem. The front-end features a Hall device and its biasing circuitry both associated to a nested chopper-like structure. This system efficiently removes 1/f noise and reduces offset. The biasing amplifier is chopped at a frequency fc in order to ensure steady ground referencing to the Hall device. This latter is operated using the spinning current technique at a frequency fs = fc/2. Sensitivities of 90 V/AT and resolutions of about 15 muT over a 1.6 kHz bandwidth extending from 5 to 1.6 kHz have been measured

A current mode CMOS IC for biological signals measurement in noisy environment

This paper describes a novel fully integrated circuit implemented in standard 0.35 ¿m CMOS technology dedicated to biological signal measurement such as ECG or EEG signals. Based on a new CMOS current conveyor (a low power 60 ¿A @ ±1.5 V power supply, 88 × 100 ¿m2 area, 100 MHz bandwidth and 10 GHz equivalent GBW circuit) the instrumentation amplifier used in this IC has a weaker offset and a better CMRR than its equivalent in Voltage mode. In order to totally cancel output offset Voltage and reduce noise, the input signal and output signal of the instrumentation amplifier are chopped at high frequency. The size and the architecture of this IC make biological signal measurement in very hostile environment such MRI, possible.

Area efficient and accurate CORDIC processor for motor control drive

The CORDIC algorithm can compute linear, trigonometric and hyperbolic functions. Mathematical identities also allow computation of other functions. Our primary aim is applications in motor control drive, such as concordia/park transform, pulse width modulation (PWM)... In this paper, we present an implementation of a fixed-point processor based on CORDIC algorithm. Large numerical errors due to such systems are eliminated by including additional hardware. We estimate the performances of our CORDIC scheme and compare it with previously proposed scheme and show that it provides a significant saving in area.

A 100 MHz Current Conveyor in 0.35 μm CMOS Technology

In this paper a new 0.35 μm CMOS technology second generation current conveyor (CCII) is presented. It is a low power (60 μA @ ± 1.5 V power supply) circuit, featuring 88 × 100 μm2 area, 100 MHz bandwidth and 10 GHz equivalent gain bandwidth (GBW) product. Its static and dynamic characteristics when used both as a voltage and current buffer are described. The chip has been fabricated and tested, and experimental results are discussed. Its use in an application as an instrumentation amplifier (IA) is also presented. The CCII based IA has weaker offset and better CMRR than its voltage mode equivalent. In order to cancel output offset voltage and reduce noise, the IAs input and output signals are chopped at high frequency.

ECG Signal Artifacts Suppression System Based on an MRI Environment Dedicated CMOS Magnetic Field Monitor and FPGA Implementation

This paper presents a system for correcting ECG signals perturbed by MRI environments. The proposed system is based on a dedicated ASIC for measuring with high resolution the MRI magnetic gradients, which are the cause of the ECG artifacts. The measured data are used to calculate the coefficients of an integration compliant adaptive LMS filter. The filter removes the artifacts from the perturbed ECG. The filter has been implemented together with a QRS complex detection algorithm on an FPGA target. The promising experimental results validate the principle and open new perspectives in terms of ASIC integration of the whole system.

An ECG signal acquisition system integrated in a 0.35 μm CMOS technology

In this paper we present an integrated ECG acquisition system implemented in a standard 0.35 μm CMOS technology. The system mainly consists of amplifiers, filters and an automatic offset compensation module. Composed of comparator, control logic and D/A converter, the compensator is an analog-digital mixed system and designed through a top-down approach. It is an independent module and can be easily reused. A low-pass filter of low cutoff frequency has been realized by using a Gm-C structure with very low bias current. Experimental measurements on the fabricated chip have been done. The results show that the integrated circuit works well with a low noise, a low consumption and a high efficacy of the offset compensator.