Vincent Frick

CMOS microsystem for AC current measurement with galvanic isolation

In this paper, we present an integrated AC current sensor based on sensitivity-optimised horizontal Hall effect devices (HHDs) and a differential readout chain. It has been designed for 5A nominal AC current measurement with 5 kV galvanic isolation and 0.5% accuracy over 1.5 kHz bandwidth, which allows up to 30/sup th/ (25 th) harmonic detection in 50 Hz (60 Hz) applications. From the sensing element to the instrumental chains output the signal conditioning is exclusively performed by low-noise standard CMOS analog blocks. Moreover the whole microsystem features a mixed signal structure dedicated to auto-balancing.

Horizontal Hall effect sensor with high maximum absolute sensitivity

Sensitivity of conventional Hall sensors is strongly limited by the well known short-circuit effect. Many researches were devoted to reduce offset and noise but few works were carried out to improve sensitivity. Here, a new shape of integrated horizontal Hall device is presented. This particular shape has been developed to minimize the short-circuit effect of the sensor, allowing one to shrink the device length and consequently to reduce the biasing resistance. Then the biasing current of this sensor can be significantly increased to obtain an absolute sensitivity higher than for conventional devices. Such a Hall effect device needs a specific biasing circuit which is also presented.

3D Hall probe integrated in 0.35 μm CMOS technology for magnetic field pulses measurements

This paper presents a 3 dimensional magnetometer based on Hall effect sensors integrated without any post processing in a standard low cost 0.35 mum CMOS technology. The system is dedicated to magnetic pulses measurements under a strong static field. Two vertical Hall devices (VHD) are sensitive to the components of the magnetic field oriented in the plane of the chip, while a horizontal Hall device (HHD) is sensitive to the component of the magnetic field orthogonally oriented to the plane of the chip. 3 identical instrumental chains are integrated to perform amplification of the 3 Hall voltages. The system implements a compensation of the static magnetic field and allows to measure magnetic fields pulses with a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth. Pulses are in the range from hundreds of muT to tens of mT in the frequency range from 1 Hz to 10 kHz. The static field is compensated up to 1.5 T. The spatial resolution is 44 mum. The system power consumption has been optimized to 15 mW.

CMOS integrated system for magnetic field monitoring and gradient measurement in MRI environment

This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.

A Vertical Hall Device in Standard Submicron CMOS Technology

In order to lower the short circuit effect due to the measurement contacts, vertical Hall devices (VHD) are generally designed either in bulky N-type silicon or in the deep N-well of high-voltage CMOS technologies. In this last case, VHD can benefit from on chip circuitry for offset and 1/f noise reduction, but HVCMOS remains a costly technology. Recently, using spinning-current, a HVCMOS compatible VHD with a resolution of 76 muT over a 1.6 kHz bandwidth has been demonstrated. The VHD presented here is designed in the shallow N-well of a low cost 0.35 mum standard CMOS technology. Unlike conventional VHD, its measurement contacts are located outside the sensor active area. FEM simulations and experimental results show that the new geometry suppresses the short circuit effect and strongly reduces the intrinsic offset and noise. Thus, without any noise and offset reduction method, this new small VHD (63 mum2) reaches a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth.

Chopper stabilized CMOS integrated front-end for magnetic field measurement

This paper presents an analogue front-end dedicated to magnetic field measurement that is intended to be used in a mixed signal submicron CMOS microsystem. The front-end features a Hall device and its biasing circuitry both associated to a nested chopper-like structure. This system efficiently removes 1/f noise and reduces offset. The biasing amplifier is chopped at a frequency fc in order to ensure steady ground referencing to the Hall device. This latter is operated using the spinning current technique at a frequency fs = fc/2. Sensitivities of 90 V/AT and resolutions of about 15 muT over a 1.6 kHz bandwidth extending from 5 to 1.6 kHz have been measured

A novel chopping-spinning MAGFET device

A novel MAGFET device is presented. Its specific architecture allows important noise reduction and thus resolution improvement by using a chopping-spinning technique performed by appropriate conditioning and read-out electronics. Experimental results have been carried out on a first non-optimized device and a sensitivity of 4 mA/T with 52 µT resolution over a bandwidth ranging from 5 Hz to 1.6 kHz have been measured.

Electromagnetically compatible CMOS auto-balanced current sensor for highly integrated power control System-On-Chip

This paper describes the design and prototyping of an auto-balanced contactless current sensor in standard Complementary Metal–Oxide–Semiconductor (CMOS) technology, without any additional post-processing cost. The architecture includes two high-sensitivity Hall plates with differential amplification electronics. A high common mode rejection is insured by the integrated auto-balancing system based on the use of integrated coils. When a common current is applied in the embedded coils, the integrated system provides a feedback signal to a digital control unit which in turn adjusts the biasing current of one of the Hall plates in order to balance the amplification of the two Hall plates. Designed in a standard CMOS technology, this sensor can be integrated in power control System-On-Chip requiring extremely electro-magnetically compatible current sensor.

High resolution, low offset Vertical Hall device in low-voltage CMOS technology

Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency performances are severely reduced by the 1/f noise. We recently proposed a theoretical study which confirm the capability of the spinning current technique to lower the 1/f noise on Low-Voltage VHD. In this paper, we proposed a practical way for the implementation of this technique. Experimental results bring out significant improvements. An offset of 0.1 mT and a resolution of 37 μT has been measured over a 1.6 kHz bandwidth.

2D MAGFET-type sensors modeling: Application to a new device design, the CHOPFET

A 2D model dedicated to MAGFET-type sensors is presented. It is applied to a new device design, the CHOPFET and dedicated to accelerating the conception of CHOPFET-based instrumentation systems. FEM Simulation show significant dependence of the geometric parameters on the devices characteristics. The model allows optimization to achieve maximum sensitivity. A compact model for CAD design is also proposed and yields satisfactory simulation results.