Jean-Philippe Delahaye

Software radio and dynamic reconfiguration on a DSP/FPGA platform

This paper discusses the implementation of modulation chains for multi-standard communications on a dynamically and partially reconfigurable heterogeneous platform. Implementation results highlight the benefit of considering a DSP/FPGA platform instead of a multi-DSP platform since the FPGA supports efficiently intensive computation components, which reduces the DSP load. Furthermore, partial dynamic reconfiguration increases the overall performance as compared to total dynamic reconfiguration since there is 45% of bitstream size reduction, which leads to a 45% decrease of the whole reconfiguration time. The implementation of modulation chains for multi-standard communications proves the availability of new technology to support efficiently Software Defined Radio.

Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

In the context of a cognitive radio terminal we propose to use partial reconfiguration of FPGAs in order to obtain a enhanced wide band software radio platform. That means the reconfiguration should be performed dynamically (during the run time). Only partial reconfiguration of FPGAs could currently meet this requirement both in terms of power computing efficiency and reconfiguration speed. In this paper we show how it is possible to perform this type of behavior within an heterogeneous platform. We consider in detail three different situations illustrated with the three following examples: the dynamical reconfiguration of a convolutional coder, a constellation mapper, and a FIR filter.

A hierarchical modeling approach in software defined radio system design

This paper presents a functional model based on a hierarchical architecture template meeting with software defined radio system requirements (SDR Systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD uplink, GSM uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of a heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.

Managing dynamic reconfiguration on MIMO Decoder

This paper is about the implementation of a MIMO V-BLAST (vertical bell laboratories layered space-time) square root decoder in a FPGA using dynamic partial reconfiguration. The decoder architecture is based on four CORDIC (coordinate rotation digital computer) units. Among these CORDIC units, three are used in rotation mode and the fourth one is used in vectoring mode. The design implementation aims power saving and area efficiency allowing dynamically changing the interconnections between the fixed modules in the reconfigurable modules. This MIMO square root design method shows the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.

A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems

This paper presents a reconfigurable Multi-Core Crypto-Processor MCCP) especially designed to secure multi-channel and multi-standard communication systems. Such component meets many constraints like high throughput and flexibility. In contrast, a classical mono-core approach either provides limited throughput or does not allow simple management of multi-channel streams. Nevertheless, parallelism is not sufficient for a multi-standard radio. It is therefore essential to increase MCCP flexibility. To achieve these results, our work takes advantage of the Xilinx FPGA hardware reconfiguration. The proposed MCCP can reach a maximum throughput of 1.7 Gbps at 190 MHz with several AES cipher modes. It uses about 4000 slices on a Virtex 4 FPGA.

A Reconfigurable Baseband Transmitter for Adaptive Image Coding

Adaptive image coding scheme are well adapted to multirate cognitive networks. A Cognitive device will be able to reconfigure itself to adapt its baseband radio transmitter to the required bit rate of the coding scheme. In this paper, a such platform able to adapt the radio access technology (RAT) to the image coding scheme is described. To optimize the RAT bit rate to the image coding bit rate, our system chooses and reconfigures in real time the radio baseband functions. It makes some cross-layer adaptation between PHY and application layers.

Predictibility of inter-component latency in a software communications architecture operating environment

This paper presents an in-depth analysis of the behavior of a SCA component-based waveform application in terms of ¿inter-component¿ communication latency. The main limitation with SCA, in the context of embedded systems, is the additional cost introduced by the use of CORBA. Previous studies have already defined the major metrics of interest regarding this issue, these are CPU cost, memory requirements and ¿inter-component¿ latency. Real-time systems can not afford high latency, in consequence, this paper focuses on this metric. The starting point of this paper is the desire of knowing if the SCA CF does not also bring an overhead. Measurements have been realized with OmniORB as CORBA distribution and OSSIE for SCA implementation. In order to perform these measurements, a SCA waveform composed of several ¿empty-components¿ have been created. ¿Empty-components¿ are software components compliant to SCA without any signal processing part. The study only focuses on communications between components. The same kind of ¿inter-component¿ link has been measured between two components using CORBA without SCA. It is possible to compare the latency values between the two measurements and to show as a result that they are approximately the same. The CORBA bus is really the part which brings an overhead to the system. The final part of this paper introduces a statistical estimation of the latency distributions. It results from measurements performed with various data packet sizes and uses a fitting method based on a combination of Gaussian functions.

Achieving SCA Conformance Testing with Model-Based Testing

The Software Communications Architecture (SCA) is a software architecture provided and published by the Joint Tactical Networking Center (JTNC). Facing the multiplicity of the waveforms and the diversity of the platform architectures and form factors, the original aims of the SCA are to facilitate the waveform development in terms of portability and waveform deployments onto heterogeneous Software Defined Radio (SDR) platforms. In this paper, we present an approach using Model-Based Testing (MBT) to ensure the conformance of a software radio platform with SCA requirements. In this approach, an MBT model is developed on the basis of SCA specifications, and conformance tests and scripts are generated and then run on the targeted software radio platform. This approach has been developed within a French research project, called OSeP, with results regarding modeling for automated test generation for SCA conformance testing. The techniques involved in this project focus on functional requirements and automatically generate Java executable test scripts, which aim to evaluate the functional conformance of the software implementation with respect to their associated requirements.