Pierre Leray

Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

In the context of a cognitive radio terminal we propose to use partial reconfiguration of FPGAs in order to obtain a enhanced wide band software radio platform. That means the reconfiguration should be performed dynamically (during the run time). Only partial reconfiguration of FPGAs could currently meet this requirement both in terms of power computing efficiency and reconfiguration speed. In this paper we show how it is possible to perform this type of behavior within an heterogeneous platform. We consider in detail three different situations illustrated with the three following examples: the dynamical reconfiguration of a convolutional coder, a constellation mapper, and a FIR filter.

A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture

A cognitive radio is the final point of software-defined radio platform evolution : a fully reconfigurable radio that changes its communication modules depending on network and/or user demands. His definition on reconfigurability is very broad and we only focus on the heterogeneous reconfigurable hardware platform for cognitive radio. software defined radio (SDR) basically refers to a set of techniques that permit the reconfiguration of a communication system without the need to change any hardware system element. The goal of Software Defined Radio is to produce communication devices which can support several different services. These terminals must adapt their hardware structure in function of the wireless networks such as GSM, UMTS, wireless LAN standards like IEEE 802.11a/b/g As a consequence, NoC offer good perspectives to future SoC in the way to satisfy SDR concept. Conception, validation and evaluation of solutions for NoC design (mapping of cores, topology, FIFO and link sizes) is conducted through simulations. We are proposing to extend the NoC structure to a FPGA where PR (Partial Reconfiguration) is used to dynamically reconfigure the requested IP block of the telecommunication chain. This work is part of our contribution for E2RII project and IDROMEL project.

A co-design methodology based on model driven architecture for real time embedded systems

This paper presents the MOPCOM design methodology, developed to enable the efficient design of real time embedded systems, in particular radio (such as software defined radio) communication and video processing equipment. Based on UML and the model driven architecture approach, it could be advantageously applied for the design of a system on a chip or a system on a programmable chip. The MOPCOM methodology defines a set of rules for building UML models for embedded systems, from which Hardware Description Language code is automatically generated by means of a set of model transformations. The MARTE profile is used to describe real time properties and to perform platform modeling. A wireless communication demonstrator is presented to illustrate the methodology and the tooling.

New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA

We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (Network on Chip) structure inside a FPGA. In the context of a SDR (Software Defined Radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology for PR management regarding the timing performances obtained in a real implementation. PR timing is a key point to make SDR approach realistic. These results show that using PR, FPGAs combine the flexibility of SW (software) and the processing power of HW (hardware). This makes PR a tremendous enabling technology for SDR. These results are based on a new IP managing the ICAP component that allows a gain in time of a rate of 124 comparing to the provided OPBHWICAP. Moreover, we have integrated a methodology which can reduce significantly the bitstream size and consequently the reconfiguration duration. The results presented in this paper show that PR reconfiguration time can go downto a few tens of microseconds. This makes PR really attractive for SDR design or any other highly demanding real-time applications.

A hierarchical modeling approach in software defined radio system design

This paper presents a functional model based on a hierarchical architecture template meeting with software defined radio system requirements (SDR Systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD uplink, GSM uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of a heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.

Managing dynamic reconfiguration on MIMO Decoder

This paper is about the implementation of a MIMO V-BLAST (vertical bell laboratories layered space-time) square root decoder in a FPGA using dynamic partial reconfiguration. The decoder architecture is based on four CORDIC (coordinate rotation digital computer) units. Among these CORDIC units, three are used in rotation mode and the fourth one is used in vectoring mode. The design implementation aims power saving and area efficiency allowing dynamically changing the interconnections between the fixed modules in the reconfigurable modules. This MIMO square root design method shows the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.

A Reconfigurable Architecture for MIMO Square Root Decoder

An implementation of reconfigurable architecture for MIMO V-BLAST (Vertical Bell Laboratories Layered Space-Time) detection based on the square root algorithm is proposed in this paper. This reconfigurable square root decoder supports MIMO system with various number of antennas, different throughputs and different signal constellations. The decoder architecture is based on various number of operators CORDIC (COordinate Rotation DIgital Computer). The system prototype of the decoder reaches 600Mbit/s data rate on an Xilinx Virtex-II FPGA for a 2 antennas system with a QPSK signal constellation.

Management architecture for green cognitive radio equipments

We assert in this paper that a management architecture has to be added to usual signal processing chain of radio equipment in order to integrate green management capabilities. The proposed architecture is based on our previous work on hierarchical and distributed cognitive radio (CR) architecture management for CR equipments. We assert that, at the level of an equipment, green radio can be considered as a subset of CR. A model-based approach is derived for the design of green radio equipments. As an example, we address in this paper a green scenario, which consists in bypassing the equaliser in function of signal to noise ratio and inter-symbol interference levels at a receiver. Then we show how we save energy, thanks to a complexity reduction. Both signal processing and implementations views are given for this scenario, which shows how our approach helps converting principles into reality. Copyright

Leakage power consumption in FPGAs: Thermal analysis

Current power saving techniques have been focused on reducing the dynamic power consumption induced by switching activity in CMOS digital circuits. Among these techniques, we can cite the clock gating, dynamic voltage frequency scaling, adaptive voltage scaling, and multiple voltage thresholds. Recently, as transistor sizes get smaller, the leakage power consumption has become a non-negligible and dominating part of the total power consumption. Thus, it is essential to take care of this new constraint in order to design low-power embedded wireless communication systems. Its well known that there are a strong relationship between leakage power and die-temperature, so that the larger leakage power consumption is associated with the higher temperature. In this paper we give a detailed analysis of FPGA leakage power consumption based on die temperature measurement. Also, after discretizing the FPGA area into several rectangular regions, we investigate whether dynamic partial reconfiguration technique can be performed over different regions to decrease average die-temperature, and consequently the leakage power consumption.

An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

This paper introduces a reconfigurable MIMO V-BLAST (vertical Bell Laboratories layered space-time) square root decoder that is CORDIC operators based, allows for dynamically changing the interconnections between the CORDIC (coordinate rotation digital computer) operators. These interconnections of CORDIC operators are implemented in a partial reconfigurable part of FPGA using the dynamic reconfiguration method which improves both the reconfiguration time and the area efficiency. Moreover, this reconfiguration time improvement is increased thanks to the MicroBlaze (within the FPGA) in which is included the reconfiguration management. This MIMO square root decoder is mapped on a Xilinx Virtex-4, showing the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.