Jean-Pierre Derutin

Ultrasonic ranging sensor using simultaneous emissions from different transducers

In recent applications based on ultrasound, several ultrasonic transducers have been geometrically and electronically associated to constitute a global sensor. There are several different methods used to process the ultrasonic signals obtained from these transducers. In this work, multimode techniques using Golay complementary sequences are proposed for processing the ultrasonic signal. The system increases scan rate, precision, and reliability. It is also capable of echo discrimination, allowing simultaneous measurements to be made and detection of the same obstacle by different transducers without cross-talk problems. The real-time implementation of the algorithm is presented on a field-programmable gate array (FPGA) device.

SKiPPER: A Skeleton-Based Parallel Programming Environment for Real-Time Image Processing Applications

This paper presents SKiPPER, a programming environment dedicated to the fast prototyping of parallel vision algorithms on MIMD-DM platforms. SKiPPER is based upon the concept of algorithmic skeletons, i.e. higher order program constructs encapsulating recurring forms of parallel computations and hiding their low-level implementation details. Each skeleton is given an architecture-independent functional (but executable) specification and a portable implementation as a generic process template. The source program is a purely functional specification of the algorithm in which all parallelism is made explicit by means of composing instances of selected skeletons, each instance taking as parameters the application specific sequential functions written in C. SKiPPER compiles this specification down to a process graph in which nodes correspond to sequential functions and/or skeleton control processes and edges to communications. This graph is then mapped onto the target topology using a third-party CAD software (SynDEx). The result is a dead-lock free, optimized (but still portable) distributed executive, which SKiPPER finally turns into executable code for the target platform. The initial specification, written in ML language, can also be executed on any sequential platform to check the correctness of the parallel algorithm. The applicability of SKiPPER concepts and tools has been demonstrated by parallelising several realistic real-time vision applications both on a multi-DSP platform and a network of workstations. It is here illustrated with a real-time vehicle detection and tracking application.

Real-time implementation of an efficient Golay correlator (EGC) applied to ultrasonic sensorial systems

Abstract Multi-mode techniques reduce scanning times in ultrasonic systems, as they allow transducers in a sensor to simultaneously emit and receive without interference. In order to implement these techniques, it is necessary to encode each transducers emission. The use of orthogonal pairs of Golay sequences associated with different emitters avoids crosstalk among them. However, these sequences imply an increase in the computational complexity required in the receiver. This paper presents the practical implementation of a system, with two emitters and four receivers, using a low-cost hardware architecture based on a FPGA. The ultrasonic signal processing is performed in real time.

Road detection and vehicles tracking by vision for an on-board ACC system in the VELAC vehicle

The paper presents a method designed to detect and track vehicles on highway in a safety improvement purpose. The goal of this kind of system is to regulate the speed of a vehicle so as to respect safety distances relative to vehicles ahead. The method is exclusively based on monocular computer vision and uses two algorithms. The first one is able to locate the lane borders in the image, and to deduce the 3D shape of the road axis. The second algorithm detects, tracks and computes the 3D location of vehicles ahead by using fixed lights embedded on these vehicles. By combining the results of the two algorithms, a fusion step permits us to know were the most dangerous vehicle is, according to its position, speed and circulation lane. The method has been implemented on our experimental vehicle VELAC and the whole system operates in real time conditions.

Design of a Scalable Network of Communicating Soft Processors on FPGA

In this work we investigate the implementation of a general parallel architecture using platform FPGA. With the implementation of communicating multiple soft processors mapped over a hypercube topology, our objective is to determine platform FPGA and SoC design environment advantages and limits for scalable multiple processors conception. We investigate the effect of communication system in FPGA devices, experimenting with different designs decisions. We present some performance results with the illustration of a parallel sort algorithm.

Fast prototyping of parallel-vision applications using functional skeletons

Abstract. We present a design methodology for real-time vision applications aiming at significantly reducing the design-implement-validate cycle time on dedicated parallel platforms. This methodology is based upon the concept of algorithmic skeletons, i.e., higher order program constructs encapsulating recurring forms of parallel computations and hiding their low-level implementation details. Parallel programs are built by simply selecting and composing instances of skeletons chosen in a predefined basis. A complete parallel programming environment was built to support the presented methodology. It comprises a library of vision-specific skeletons and a chain of tools capable of turning an architecture-independent skeletal specification of an application into an optimized, deadlock-free distributive executive for a wide range of parallel platforms. This skeleton basis was defined after a careful analysis of a large corpus of existing parallel vision applications. The source program is a purely functional specification of the algorithm in which the structure of a parallel application is expressed only as combination of a limited number of skeletons. This specification is compiled down to a parametric process graph, which is subsequently mapped onto the actual physical topology using a third-party CAD software. It can also be executed on any sequential platform to check the correctness of the parallel algorithm. The applicability of the proposed methodology and associated tools has been demonstrated by parallelizing several realistic real-time vision applications both on a multi-processor platform and a network of workstations. It is here illustrated with a complete road-tracking algorithm based upon white-line detection. This experiment showed a dramatic reduction in development times (hence the term fast prototyping), while keeping performances on par with those obtained with the handcrafted parallel version.

Road Detection and Vehicle Tracking by Vision for Adaptive Cruise Control

This article deals first with a process designed to detect the circulation lane of a vehicle by onboard monocular vision. This detection process is based on a recursive updating of a statistical model of the lane obtained by a training phase. Once the lane has been located, a reconstruction algorithm computes the vehicle location on its lane and the three-dimensional shape of the road. Thereafter, the authors seek to detect and track vehicles situated in front of their vehicle and equipped with specific visual markers in order to achieve an accurate determination of their location and speed. By combining these various data, the most dangerous obstacle can be identified. Each of these three processes is described in detail, and significant examples are provided.

A MP-SoC design methodology for the fast prototyping of embedded image processing system

This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve highperformance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new design flow that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

SIMD, SMP and MIMD-DM parallel approaches for real-time 2D image stabilization

We present a real-time image stabilization method, based on a 2D motion model and different levels of parallel implementation. This stabilization method is decomposed into three main parts. First, the image matching is determined by a feature-based technique, then the motion between consecutive frames is estimated and filtered to extract the unwanted motion component. This component is finally used to correct (warp) the images, resulting in a stable sequence. To validate our stabilization approach in a real-time on-board system context, the algorithm was implemented and tested over different hardware platforms, allowing a performance evaluation in function of the adopted architecture. In this paper, we present some of the results, concerning the parallel implementation of the algorithm, using the MW ALTIVEC/spl reg/ instructions set, a symmetric multi-processor (SMP) architecture and MIMD-DM architecture.