Cesar Roda Neve

RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.

RF MEMS Passives on High-Resistivity Silicon Substrates

Diverse RF passive devices and microelectro- mechanical systems (MEMS) can be monolithically integrated on a high-resistivity silicon (HR-Si) substrate. However, parasitic surface conduction (PSC) at the interface of HR-Si and a silicon dioxide (SiO2) passivation layer reduces the effective substrate resistivity, which in turn results in deterioration of the device quality factor (Q) and non-linearity. Trap-rich HR-Si has been proposed as a low substrate loss alternative, eliminating the problems associated with PSC. However, the full potential of trap-rich HR-Si as a common platform for implementing MEMS passives is not fully explored. In this letter, we evaluate the effectiveness of the trap-rich layer by comparing the frequency response of a number of RF passive devices fabricated on standard and trap-rich HR-Si substrates. In addition, we suggest an electromagnetic (EM) simulation setup that can be used to efficiently and accurately simulate the device performance.

Nonlinear Properties of Si Based Substrates for Wireless Systems and SoC Integration

The nonlinear behaviour of silicon substrates with different resistivities is analyzed using coplanar structures. In order to compare the nonlinear performance for different substrates and technologies, the harmonic distortion of crosstalk test structures is investigated, as well as the dependence on the distance. The generated harmonic components due to a large signal at 900 MH are measured using a one-tone network analyzer based setup. Below the crosstalk tap, harmonic levels as high as -43 and -54 dBc for 15 dBm are generated for standard and high-resistivity (HR) Si substrate, respectively. The introduction of a trap-rich layer at the interface between the BOX and the high-resistivity Si (HR-Si) provides a reduction of at least 45 dB in the harmonic distortion generated into the substrate. It has been proven that these results can be easily extrapolated to crosstalk structures with different dimensions.

Fabrication and characterization of High Resistivity SOI wafers for RF applications

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed when the substrate surface is passivated with a trap-rich layer of material, such as polysilicon. A technique to fabricate substrate-passivated HR SOI wafer is presented, where the wafers are obtained by bonding a polysilicon-passivated HR Si substrate with an oxidized donor substrate. Preliminary encouraging bonding test results are presented.

Technology optimization for high bandwidth density applications on 3D interposer

3D interposers are one of just a few ways of making electronic systems faster and more powerful, but their design can be complex. This paper presents a optimization flow to assist the design of silicon interposers with the highest bandwidth density possible. Using the methodology described in this paper, simulations have shown that chip-to-chip links on a silicon interposer can achieve bandwidth densities between 250Gbps/mm and 4.5Tbps/mm depending on a wide range of parameters such as interconnect length, interlayer dielectric (ILD) material and micro-bump pitch.

A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

A 3D-integrated test vehicle that emulates noise generation and propagation in a heterogeneous integrated system has been developed. In-stack waveform capturers are embedded on each tier which captured the generation and propagation of noise. A consistent analytical model is created and analysis using that model has allowed us to develop a design strategy for the power delivery network to attenuate noise propagation in the stacked system.

Photo-Induced Coplanar Waveguide RF Switch and Optical Crosstalk on High-Resistivity Silicon Trap-Rich Passivated Substrate

A continuous-wave mode optically controlled coplanar waveguide radio frequency (RF) switch on high-resistivity silicon substrate with and without trap-rich polysilicon (poly-Si) layer is investigated. Because of the local poly-Si trap-rich layer, we experimentally show the important reduction of optical crosstalk without degrading the photo-controlled RF switch performance. A photo-induced plasma confinement by locally etching the poly-Si layer to control the photogenerated free carriers and their lateral diffusion is realized. Optical crosstalk between two coplanar waveguide RF switches is reduced by at 20 GHz.

ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package

Adding low-cost front-end processing to a passive interposer process flow enables the low-cost processing of diodes, SCRs and bipolar transistors. Using those devices in an ESD protection design allows moving a large part of the ESD protection from the stacked die to the interposer.