Jean Simatic

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept

A new fully digital high resolution time-to-digital converter (TDC) based on a self-timed ring oscillator (STR) is presented. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. The TDC has been implemented using 28 nm FDSOI technology to provide a proof of concept of the proposed method. Simulation results point out the advantage of this TDC in terms of measurement accuracy.

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines

This paper presents two new area-reduced controllers for bundled-data asynchronous pipelines in which the stages have long critical paths. The proposed protocols allow to reduce the number of required delay elements by using the falling edge of the asynchronous request to indicate data validity. For critical path lengths of 25 gates, the first presented scheme decreases the controller area by 48% and slightly increases the maximum throughput (2%) in comparison to a standard micropipeline implementation. The other more-concurrent scheme proposition leads to a 25% area reduction and a 40% improvement of the maximum pipeline throughput.

High-level synthesis for event-based systems

This paper envisions a design flow for empowering designers in the fast development of low-power event-driven processing chains. This flow takes advantage of level-crossing sampling schemes and asynchronous circuitry. Event-driven paradigm allows better-than-worst-case performance during periods of high-activity of the captured signal as well as a natural stand-by during low-activity periods. The proposed flow uses the specific knowledge of the targeted application and its signals, and a high-level description of the processing algorithm to synthesize a dedicated analog-to-digital converter, which performs the level-crossing sampling, and a digital signal processing unit. The latter is synthesized thanks to a high-level synthesis algorithm following a control/datapath decomposition style. The asynchronous control part is based on distributed asynchronous controllers while the datapath remains similar to a synchronous datapath.

Seeking low-power synchronous/asynchronous systems: A FIR implementation case study

Seeking low-power consumption high-performance embedded systems has been at the center of interest for researchers around the world for the last decades, especially with the recent boom of different hand-held battery-operated mobile connected devices. The new trends and needs of faster, smarter and smaller internet connected systems, also known as the IoT, require developing very-low power embedded systems including actuators, sensors and signal processors. In this paper, we focus on the architecture optimization efforts to reduce the required activity using the FIR filter as a demonstration example. The new optimized implementation of the FIR filter was compared with other synchronous and asynchronous FIR filter versions realized using the ALPS framework developed at TIMA laboratory. The obtained FIR architecture exhibits 43% less area and up to 61% power consumption reduction compared to the best previous synchronous implementation. We plan to use these results to improve the automatically generated datapath of the high-level synthesis tool of our framework (ALPS-HLS).

High-level synthesis of an event-driven windowing process

This work is a contribution to enhance the signal processing chain required in modern systems. The idea is to take advantage of the interesting features of both event-driven and well-established uniform sampling and signal processing algorithms. In this context, authors have proposed original windowing techniques for the event-driven sampled signal, activity selection and local parameter extraction. These are called as Activity Selection Algorithms (ASA). The proposed techniques correlate the windowing function length, shape and resampling frequency with the input signal time variations. In this paper, the ASA and an adaptive rate resampler with zero order interpolation are implemented in C. Using high level synthesis tools, synchronous and asynchronous register transfer level descriptions are synthesized on a commercial CMOS 40 nm technology. The synthesis results are presented. A comparison of the average power consumption between asynchronous and synchronous implementations is made. The proposed system functionality is also verified with the help of analytic test signals. Results have shown a compression, in terms of samples, of 1.5 to 1.6 respectively compared to the simple event-driven level-crossing sampling and by 5.8 to 9.3 compared to the uniform sampling based systems. The asynchronous (resp. synchronous) implementation of ASA and resampler only consumes in average 28pJ/sample (resp. 238 pJ/sample).

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines

Asynchronous circuits are interesting alternatives for implementing ultra-low power systems but they are more challenging to design. This work provides methods for designers to specify, verify, and implement self-timed pipelines. The connection of standard primitives allows specifying a control circuit. A method to derive a Petri net based model of this circuit is presented. The modeled transactions are only those necessary at a high level for the circuit verification and performance analysis. Additionally, the proposed framework includes merge and split choice structures in the control circuit for further reducing the power consumption of the targeted systems. It is associated with a design flow which uses standard EDA tools. The paper presents two practical examples illustrating how this framework can be used to design low-power systems based on a datapath specification: a finite impulse response (FIR) filter and an advanced encryption standard (AES) cipher. The obtained asynchronous FIR is 20% smaller and consumes 30% less energy compared to the synchronous design. The obtained asynchronous AES is 2% larger but consumes three times less energy than its synchronous counterpart.

Correctly sizing FIR filter architecture in the framework of non-uniform sampling

Based on non-uniform sampling techniques and event-driven logic, signal processing is evolving to integrate new demands such as power consumption. As power is mainly connected to the processing activity and data volume, the level-crossing sampling scheme offers a simple way to reduce data volume and consequently processing activity. Nevertheless, these good properties could be constraining for the designers because of the non-predictable sample number that can be involved in the processing. In this paper, we target a FIR filter architecture and show how to correctly size its input shift-register. This paper shows a strategy to choose the shift-register depth but also a way to dynamically adapt the computation to an heterogeneous data flow.